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    Programmable communicating finite state machines with mealy communication behaviour
    12.
    发明专利
    Programmable communicating finite state machines with mealy communication behaviour 未知

    公开(公告)号：GB2461649A

    公开(公告)日：2010-01-13

    申请号：GB0913420

    申请日：2009-08-03

    Applicant: IBM

    Inventor： SCHLIPF THOMAS ,  FRITZ ROLF ,  SMITH CHRISTOPHER S ,  MAYER ULRICH ,  LUNTEREN JAN VAN

    IPC: G05B19/045

    Abstract: Preventing a communication loop in communicating finite state machines by providing two tables, an output next state (OTNS) table and a communication output (COUT) table. The OTNS table is divided into two array data structures, an input compare vector (ICVT1) and an output next state next address table (ONNT). The COUT table is divided into two array data structures, an input compare vector (ICVT2) and a communication output table (COMCONT). Input compare vectors in the ICVT1 are retrieved and fed into comparators. The comparators compare the retrieved input compare vectors with an input signal. When a match is found, a corresponding comparator sets a corresponding selection signal to a pre-determined value to generate an offset value through a multiplexer. An adder adds the offset value and a value stored in a current state start address (CSSA) register, and generates an adding result. The adding result is used as an address to access a row in the ONNT. There is state transition information in that row of the ONNT.

    Updating corrupted local working registers in a multi-staged pipelined execution unit by refreshing from the last state hold a global checkpoint array
    13.
    发明专利
    Updating corrupted local working registers in a multi-staged pipelined execution unit by refreshing from the last state hold a global checkpoint array 未知

    公开(公告)号：GB2456891A

    公开(公告)日：2009-08-05

    申请号：GB0823186

    申请日：2008-12-19

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  MAYER ULRICH ,  LEHNERT FRANK ,  SHUM KEVIN CHUNG-LUNG

    IPC: G06F9/38 ,  G06F11/00

    Abstract: Disclosed is a method for updating corrupted local working registers in a multi-staged pipeline structure, after an exception. The registers being needed to execute complex instructions in an execution unit, e.g. a floating-point unit, whose deep pipeline structure comprises a set of local working registers. The pipeline being such data dependencies among different instructions referencing the same registers exist. The method operates by refreshing any corrupted local working register from the last architected state hold in a global checkpoint array. The registers may also be updated using the hardware infrastructure of the execution unit when the data is corrupted by early pipeline updates. A master copy of all local working registers may be held in the checkpoint array, which is not updated in exception cases. All the early loads or early register updates form instructions that were issued after an instruction got into the exception may be refreshed.

    Clock gating system for macro circuits on a semiconductor chip
    14.
    发明专利
    Clock gating system for macro circuits on a semiconductor chip 未知

    公开(公告)号：GB2456202A

    公开(公告)日：2009-07-08

    申请号：GB0821970

    申请日：2008-12-02

    Applicant: IBM

    Inventor： GERWIG GUENTER ,  LEHNERT FRANK ,  MAYER ULRICH

    IPC: G06F1/10 ,  G06F1/32

    Abstract: A digital circuit on a semiconductor chip comprises a plurality of macro circuits (10, 12, 14) and a clock gating system (50, 52, 54) for disabling the clock signal for at least one single macro circuit (12) to reduce power consumption. The circuit comprises a hierarchical structure with at least two clock gating levels, and each macro circuit (10, 12, 14) is associated with one of the levels. A macro control circuit (10) is provided on a top clock gating level and controls the clock gating of at least one other macro circuit (12) on one or more lower clock gating levels, wherein all external signals used to control the clock gating are connected to the control circuit (10). The method distinguishes between two clock gating granularities. A coarse-grain gating operates on the boundaries of the macro circuits, and a fine-grain gating operates mainly on dataflow storage elements within the macro circuits.

    Progammable two table indexed finite state machine
    18.
    发明专利
    Progammable two table indexed finite state machine 未知

    公开(公告)号：GB2461648A

    公开(公告)日：2010-01-13

    申请号：GB0913415

    申请日：2009-08-03

    Applicant: IBM

    Inventor： SCHLIPF THOMAS ,  FRITZ ROLF ,  SMITH CHRISTOPHER S ,  MAYER ULRICH ,  LUNTEREN JAN VAN

    IPC: G05B19/045

    Abstract: A system stores an input compare vector in an input compare vector table. The system also stores an output vector, a next state value and a next state start address in an output vector, next state, next state address table. Each comparator compares each input compare vector from the input compare vector table and an external input vector, and outputs a selection signal to a multiplexer. The multiplexer associates the selection signals with an offset value, and provides the offset value to adder logic. The adder logic adds the offset value and an address from a current state start address register. A result of the addition is used as an address to access a row in the output vector, next state, next state address table. The accessed row has an output vector, a next state value and a next state start address corresponding to a current state and the external input vector.

    Controlling timeouts of an error recovery procedure in a digital circuit
    19.
    发明专利
    Controlling timeouts of an error recovery procedure in a digital circuit 未知

    公开(公告)号：GB2456656A

    公开(公告)日：2009-07-29

    申请号：GB0822778

    申请日：2008-12-15

    Applicant: IBM

    Inventor： MAYER ULRICH ,  LEHNERT FRANK ,  GERWIG GUENTER ,  SWANEY SCOTT BARNETT

    IPC: G06F11/07 ,  G06F9/38

    Abstract: The invention relates to apparatus for controlling timeouts and delays of an error recovery procedure in a digital circuit, e.g. a microprocessor. The apparatus comprises a finite state machine (FSM) 10, having a plurality of states 12 and a plurality of transitions 14. Transitions 14 are arranged between two states 12 respectively. States 12 correspond with operation steps (40, 44, 52, 56, 58, 64) of the error recovery procedure, including error classification, a drain operation, a fence operation in which a microprocessor core does not communicate with memory, a reset or refresh operation, and automatic built-in self test (ABIST). Transitions 14 of the FSM 10 depend on conditions (46, 50, 53, 57, 59, 62) for the error recovery procedure. The FSM 10 is coupled with a timeout logic circuit 20 which controls a timer to obtain the timeouts (46, 53, 57, 59) of the error recovery procedure. The FSM is configurable by a data vector which describes states 12 of the FSM for which the timer should be engaged.

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