公开(公告)号：SG174129A1

公开(公告)日：2011-10-28

申请号：SG2011057288

申请日：2010-03-29

Applicant: IBM

Inventor： BU HUIMING ,  CHUDZIK MICHAEL P ,  HE WEI ,  JHA RASHMI ,  KIM YOUNG-HEE ,  KRISHNAN SIDDARTH A ,  MO RENEE T ,  MOUMEN NAIM ,  NATZLE WESLEY C

Abstract: A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.

公开(公告)号：MX2011008338A

公开(公告)日：2011-09-01

申请号：MX2011008338

申请日：2010-03-29

Applicant: IBM

Inventor： BU HUIMING ,  CHUDZIK MICHAEL P ,  HE WEI ,  JHA RASHMI ,  KIM YOUNG-HEE ,  KRISHNAN SIDDARTH A ,  MO RENEE T ,  MOUMEN NAIM ,  NATZLE WESLEY C

IPC: H01L21/336

Abstract: El método para formar un dispositivo incluye proporcionar un sustrato, formar una capa interfacial sobre el sustrato, depositar una capa dieléctrica de k alta sobre la capa interfacial, depositar una capa depuradora de oxígeno sobre la capa dieléctrica de k alta y efectuar un recocido. Un transistor de compuerta de metal de k alta incluye un sustrato, una capa interfacial sobre el sustrato, una capa dieléctrica de k alta sobre la capa interfacial y una capa depuradora de oxígeno sobre la capa dieléctrica de k alta.

公开(公告)号：GB2488421B

公开(公告)日：2013-11-20

申请号：GB201202928

申请日：2010-10-26

Applicant: IBM

Inventor： MOUMEN NAIM ,  MARTIN YVES ,  KESSEL THEODORE GERARD VAN ,  SANDSTROM ROBERT ,  GUHA SUPRATIK

IPC: H01L31/0224 ,  H01L31/0687

Abstract: Electrical contact to the front side of a photovoltaic cell is provided by an array of conductive through-substrate vias, and optionally, an array of conductive blocks located on the front side of the photovoltaic cell. A dielectric liner provides electrical isolation of each conductive through-substrate via from the semiconductor material of the photovoltaic cell. A dielectric layer on the backside of the photovoltaic cell is patterned to cover a contiguous region including all of the conductive through-substrate vias, while exposing a portion of the backside of the photovoltaic cell. A conductive material layer is deposited on the back surface of the photovoltaic cell, and is patterned to form a first conductive wiring structure that electrically connects the conductive through-substrate vias and a second conductive wiring structure that provides electrical connection to the backside of the photovoltaic cell.

公开(公告)号：GB2488421A

公开(公告)日：2012-08-29

申请号：GB201202928

申请日：2010-10-26

Applicant: IBM

Inventor： MOUMEN NAIM ,  MARTIN YVES ,  KESSEL THEODORE GERARD VAN ,  SANDSTROM ROBERT ,  GUHA SUPRATIK

IPC: H01L31/0224 ,  H01L31/0687

Abstract: Electrical contact to the front side of a photovoltaic cell is provided by an array of conductive through-substrate vias, and optionally, an array of conductive blocks located on the front side of the photovoltaic cell. A dielectric liner provides electrical isolation of each conductive through-substrate via from the semiconductor material of the photovoltaic cell. A dielectric layer on the backside of the photovoltaic cell is patterned to cover a contiguous region including all of the conductive through-substrate vias, while exposing a portion of the backside of the photovoltaic cell. A conductive material layer is deposited on the back surface of the photovoltaic cell, and is patterned to form a first conductive wiring structure that electrically connects the conductive through-substrate vias and a second conductive wiring structure that provides electrical connection to the backside of the photovoltaic cell.

公开(公告)号：CA2750282A1

公开(公告)日：2010-10-07

申请号：CA2750282

申请日：2010-03-29

Applicant: IBM

Inventor： BU HUIMING ,  CHUDZIK MICHAEL P ,  HE WEI ,  JHA RASHMI ,  KIM YOUNG-HEE ,  KRISHNAN SIDDARTH A ,  MO RENEE T ,  MOUMEN NAIM ,  NATZLE WESLEY C

IPC: H01L21/283 ,  H01L21/285 ,  H01L21/324 ,  H01L29/40 ,  H01L29/43

Abstract: A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.

公开(公告)号：DE112004000745B4

公开(公告)日：2008-05-29

申请号：DE112004000745

申请日：2004-05-06

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BEINTNER JOCHEN ,  LI YUJUN ,  MOUMEN NAIM ,  WRSCHKA PORSHIA SHANE

IPC: H01L29/423 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

Abstract: The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g. source and drain implants, extension implants, and pocket lightly doped drain (LDD) implants), gate conductor stack doping, and silicidation are preferably performed in completing the transistor.

公开(公告)号：DE112004000745T5

公开(公告)日：2006-06-08

申请号：DE112004000745

申请日：2004-05-06

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BEINTNER JOCHEN ,  LI YUJUN ,  MOUMEN NAIM ,  WRSCHKA PORSHIA SHANE

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/265 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

Abstract: The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g. source and drain implants, extension implants, and pocket lightly doped drain (LDD) implants), gate conductor stack doping, and silicidation are preferably performed in completing the transistor.