公开(公告)号：MY117869A

公开(公告)日：2004-08-30

申请号：MYPI9705190

申请日：1997-11-03

Applicant: IBM

Inventor： GARBELLI FRANCESCO ,  MONTI ALBERTO ,  OGGIONI STEFANO

IPC: H01L21/68 ,  H01L23/13 ,  H01L23/31 ,  H05K1/14 ,  H05K3/30 ,  H05K7/12

Abstract: IN THE MANUFACTURING PROCESS OF ELECTRONIC MODULES A PROBLEM COULD ARISE WHEN THE MODULES HAVE NON-FLAT TOP SURFACE. THIS IS DUE TO THE FACT THAT MOST OF THE AUTOMATIC PICKING TOOLS USES A VACUUM NOZZLE TO PICK AND PLACE THE MODULE. ACCORDING TO THE PRESENT INVENTION A FLAT FEATURE(301) (A CAP OR A STUD) IS ADDED TO THE MODULE(101). THIS FLAT FEATURE CAN BE EITHER FIXED ON THE MODULE OR REMOVABLE AFTER THE MANUFACTURE IN ORDER TO REDUCE THE DIMENSIONS. (FIG.3)

公开(公告)号：CA2222602C

公开(公告)日：2003-06-24

申请号：CA2222602

申请日：1997-11-27

Applicant: IBM

Inventor： OGGIONI STEFANO ,  GARBELLI FRANCESCO ,  MONTI ALBERTO

IPC: H01L21/68 ,  H01L23/31 ,  H05K1/14 ,  H05K3/30 ,  H05K13/04

Abstract: In the manufacturing process of electronic modules a problem could arise whe n the modules have non-flat top surface. This is due to the fact that most of the automati c picking tools uses a vacuum nozzle to pick and place the module. According to the present inventi on a flat feature (a cap or a stud) is added to the module. This flat feature can be either fixed on the module or removable after the manufacture in order to reduce the dimensions.

公开(公告)号：CA2222602A1

公开(公告)日：1998-06-04

申请号：CA2222602

申请日：1997-11-27

Applicant: IBM

Inventor： OGGIONI STEFANO ,  GARBELLI FRANCESCO ,  MONTI ALBERTO

IPC: H01L21/68 ,  H01L23/31 ,  H05K1/14 ,  H05K3/30 ,  H05K13/04

Abstract: In the manufacturing process of electronic modules a problem could arise whe n the modules have non-flat top surface. This is due to the fact that most of the automati c picking tools uses a vacuum nozzle to pick and place the module. According to the present inventi on a flat feature (a cap or a stud) is added to the module. This flat feature can be either fixed on the module or removable after the manufacture in order to reduce the dimensions.

公开(公告)号：DE60314868T2

公开(公告)日：2008-03-13

申请号：DE60314868

申请日：2003-04-18

Applicant: IBM

Inventor： CASTRIOTTA MICHELE ,  OGGIONI STEFANO ,  ROGIANI GIANLUCA ,  SPREAFICO MAURO ,  VIERO GIORGIO

IPC: H05K1/11 ,  H01L23/498 ,  H05K3/46 ,  H01L23/538 ,  H01L23/66 ,  H05K1/02

Abstract: A stacked via structure ( 200 ) adapted to transmit high frequency signals or high intensity current through conductive layers of an electronic device carrier is disclosed. The stacked via structure comprises at least three conductive tracks ( 205 a, 205 b, 205 c) belonging to three adjacent conductive layers ( 110 a, 110 b, 110 c) separated by dielectric layers ( 120 ), aligned according to z axis. Connections between these conductive tracks are done with at least two vias ( 210, 215 ) between each conductive layer. Vias connected to one side of a conductive track are disposed such that they are not aligned with the ones connected to the other side according to z axis.

公开(公告)号：GB2368454B

公开(公告)日：2005-04-06

申请号：GB0025985

申请日：2000-10-24

Applicant: IBM

Inventor： OGGIONI STEFANO ,  RAVANELLI ROBERTO

IPC: H01L23/498 ,  H01L23/552 ,  H01L23/66

Abstract: An electronic package is provided. The electronic package includes a chip carrier having a first conductive layer which includes at least one signal track and at least one contact area, the contact area being electrically connected to the signal track and adapted for transmitting a high-frequency signal. The chip carrier further includes a reference structure having at least two conductive layers such that the signal track is electrically shielded by the reference structure. A semiconductor chip is positioned on the chip carrier and includes at least one terminal electrically interconnected to the at least one contact area.

公开(公告)号：GB2368454A

公开(公告)日：2002-05-01

申请号：GB0025985

申请日：2000-10-24

Applicant: IBM

Inventor： OGGIONI STEFANO ,  RAVANELLI ROBERTO

IPC: H01L23/498 ,  H01L23/552 ,  H01L23/66

Abstract: A chip carrier (110) for a high-frequency electronic device (100) has a circuitised substrate (115) with a plurality of conductive layers (210a-210d) insulated from each other. The conductive layers are arranged in a sequence. A first one of the conductive layers (210a) has a plurality of signal tracks (104s) each one ending with a contact area (145s) for transmitting a high-frequency signal. A reference structure (215g,225g,140ch,140cl) is connectable to a reference voltage for shielding the signal tracks. The reference structure includes at least one reference track (215g) formed in a second one of the conductive layers (210b) adjacent to the first conductive layer and at least one further reference track (225g) is formed in one of the conductive layers (210d) different from the first and second conductive layer. A portion of each signal track excluding the contact area is superimposed in plan view to a corresponding reference track and the contact area of each signal track is superimposed in plan view to a corresponding further reference track without interposition of any other of the conductive layers (210a-210c).

公开(公告)号：GB2358957A

公开(公告)日：2001-08-08

申请号：GB9925318

申请日：1999-10-27

Applicant: IBM

Inventor： OGGIONI STEFANO ,  VENDRAMIN GIUSEPPE

IPC: H01L23/498 ,  H01L23/552 ,  H01L23/488 ,  H05K1/05

Abstract: A Ball Grid Array electronic package of the Cavity Down type for use in HF application comprises a thin dielectric layer 403 laid on a stiffener 401 made from a metal such as copper. Circuit traces are laid on the dielectric layer 403 and have one end connected to an active element 407 mounted on the same side of the dielectric layer 403 and the other end connected to solder balls 411 for connecting the active element 407 to the mother board. Peripherally to the traces, metallised photovias are connected to the metal stiffener 401 , which acts as a ground plane, and solder balls 413 for connection with the mother board to realise the lateral shielding for HF applications. The package leads to a dramatic reduction in pirasitic impedence and allows a reduction in the overall thickness of the package.

公开(公告)号：GB2504343A

公开(公告)日：2014-01-29

申请号：GB201213365

申请日：2012-07-27

Applicant: IBM

Inventor： BRUNSCHWILER THOMAS J ,  GOICOCHEA JAVIER V ,  OGGIONI STEFANO ,  SCHLOTTIG GERD

IPC: H01L21/56

Abstract: A method for manufacturing an underfill in a semiconductor chip stack having a cavity 4 between a first surface (2, figure 1) and a second surface (3). The cavity has multiple access 109 and vent 110 holes in at least one of the said surfaces. Viscous filling material (13) is applied through the access hole into the cavity thereby squeezing air or gas through the vent holes. The filler material may comprise of a carrier fluid 16 and filler particles 17, and be applied to the access holes by way of a dispenser tube 14. The filler material occupies the space within the cavity such that it surrounds solder balls 7. Once the filler material fills the cavity between a particular access hole and vent hole the filler material may instead be inserted through said vent hole. The vent holes may also comprise a filter element which restricts the filler particles 17 from exiting the cavity.

公开(公告)号：GB2358957B

公开(公告)日：2004-06-23

申请号：GB9925318

申请日：1999-10-27

Applicant: IBM

Inventor： OGGIONI STEFANO ,  VENDRAMIN GIUSEPPE

IPC: H01L23/498 ,  H01L23/552 ,  H01L23/488 ,  H05K1/05

Abstract: A Plastic Ball Grid Array electronic package of the Cavity Down type for use in HF application. The present invention allows to reduce the overall thickness of the package, by tailoring the different mechanical portions of the module structure (interconnection balls, grounded stiffener thickness). A thin dielectric layer is laid on a metal (e.g. copper) stiffener. A chip is attached on the same side of the dielectric layer and the electrical connections between the chip and the pads are done with metallic traces running on the surface of the dielectric layer. The external rows of balls are not connected to the circuit traces; they are electrically connected to the metal stiffener to realize the lateral shielding for the HF applications. The connection between the balls and the metal stiffener (which acts as the ground plane) is done by means of photovias. One of the more important aspects of the present invention is the dramatic reduction of the parasitic impedance.

公开(公告)号：AU2003276277A1

公开(公告)日：2004-03-03

申请号：AU2003276277

申请日：2003-04-18

Applicant: IBM

Inventor： CASTRIOTTA MICHELE ,  OGGIONI STEFANO ,  ROGIANI GIANLUCA ,  SPREAFICO MAURO ,  VIERO GIORGIO

IPC: H05K3/46 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H05K1/02 ,  H05K1/11

Abstract: A stacked via structure ( 200 ) adapted to transmit high frequency signals or high intensity current through conductive layers of an electronic device carrier is disclosed. The stacked via structure comprises at least three conductive tracks ( 205 a, 205 b, 205 c) belonging to three adjacent conductive layers ( 110 a, 110 b, 110 c) separated by dielectric layers ( 120 ), aligned according to z axis. Connections between these conductive tracks are done with at least two vias ( 210, 215 ) between each conductive layer. Vias connected to one side of a conductive track are disposed such that they are not aligned with the ones connected to the other side according to z axis.