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    11.
    发明专利
    未知

    公开(公告)号：AT327555T

    公开(公告)日：2006-06-15

    申请号：AT01995491

    申请日：2001-12-10

    Applicant: IBM

    Inventor： BARTH JOHN E JR ,  PILO HAROLD

    IPC: G11C11/407 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/00

    Abstract: A system and method is disclosed for writing early within a memory cycle by holding only one of a true bitline and a reference bitline at a fixed potential, e.g. ground, when the sense amplifier is set. The sense amplifier amplifies a small voltage difference between the true bitline and the reference bitline to predetermined high and low voltage logic levels to write a datum to the memory cell. In this way, writing can complete in about the same time as reading, without risking corruption of data on adjacent bitlines in the memory. The bitlines are precharged to a fixed potential in a conduction path through the bitswitches, rather than using local precharge devices at the sense amplifier. To write, bitswitches and write path transistors apply the fixed potential to one of the true bitline and the reference bitline. Bitswitches on such other memory cells not currently being written isolate the bitline pairs coupled to those memory cells when setting the sense amplifiers, such that the stored contents of such memory cells not being written are refreshed (written back) at the time that the selected memory cell is written.

    Feingranulares Power-Gating
    13.
    发明专利
    Feingranulares Power-Gating 未知

    公开(公告)号：DE102012217578A1

    公开(公告)日：2013-06-13

    申请号：DE102012217578

    申请日：2012-09-27

    Applicant: IBM

    Inventor： HOULE ROBERT M ,  LAMPHIER STEVEN H ,  PILO HAROLD

    IPC: G11C5/14

    Abstract: Ein Ansatz zum Bereitstellen eines feingranularen Power-Gating eines Speicher-Array wird beschrieben. In einer Ausführungsform sind Stromversorgungsleitungen in einer horizontalen Erstreckung des Speicher-Array parallel zu den Wortleitungen angeordnet, die auf die Zellen zugreifen, die in Zeilen und Spalten des Array angeordnet sind, wobei jede der Versorgungsleitungen durch benachbarte Zellen in dem Speicher gemeinsam verwendet wird. Stromversorgungsleitungen, die eine durch eine der Wortleitungen ausgewählte Zeile aktivieren, werden mit einem vollen Spannungswert versorgt, und Stromversorgungsleitungen, die Zeilen aktivieren, die zu der ausgewählten Zeile benachbart sind, werden mit einem halben Spannungswert versorgt, während die Stromversorgungsleitungen der restlichen Zeilen in dem Speicher-Array mit einem durch Power-Gating gesteuerten Spannungswert versorgt werden.

    14.
    发明专利
    未知

    公开(公告)号：DE60119995T2

    公开(公告)日：2007-05-24

    申请号：DE60119995

    申请日：2001-12-10

    Applicant: IBM

    Inventor： BARTH E ,  PILO HAROLD

    IPC: G11C7/00 ,  G11C11/407 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4094

    Abstract: A system and method is disclosed for writing early within a memory cycle by holding only one of a true bitline and a reference bitline at a fixed potential, e.g. ground, when the sense amplifier is set. The sense amplifier amplifies a small voltage difference between the true bitline and the reference bitline to predetermined high and low voltage logic levels to write a datum to the memory cell. In this way, writing can complete in about the same time as reading, without risking corruption of data on adjacent bitlines in the memory. The bitlines are precharged to a fixed potential in a conduction path through the bitswitches, rather than using local precharge devices at the sense amplifier. To write, bitswitches and write path transistors apply the fixed potential to one of the true bitline and the reference bitline. Bitswitches on such other memory cells not currently being written isolate the bitline pairs coupled to those memory cells when setting the sense amplifiers, such that the stored contents of such memory cells not being written are refreshed (written back) at the time that the selected memory cell is written.

    Dual power supply memory array with dynamic selection of the lowest voltage
    15.
    发明专利
    Dual power supply memory array with dynamic selection of the lowest voltage 未知

    公开(公告)号：GB2497180B

    公开(公告)日：2013-11-13

    申请号：GB201220563

    申请日：2012-11-15

    Applicant: IBM

    Inventor： PILO HAROLD ,  BRACERAS GEORGE MARIA ,  PETERSON KIRK DAVID

    IPC: G11C11/412 ,  G11C5/14 ,  G11C7/12 ,  G11C11/417

    Abstract: Disclosed is a memory array in which the lower of two supply voltages from two power supplies is dynamically selected for bitline pre-charge operations. In the memory array, a voltage comparator compares the first supply voltage on a first power supply rail to a second supply voltage on a second power supply rail and outputs a voltage difference signal. If the voltage difference signal has a first value indicating that the first supply voltage is equal to or less than the second supply voltage, than a control circuit ensures that the complementary bitlines connected to a memory cell are pre-charged to the first supply voltage. If the voltage difference signal has a second value indicating that the first supply voltage is greater than the second supply voltage, then the control circuit ensures that the complementary bitlines are pre-charged to the second supply voltage. Also disclosed is an associated method.

    Dual power supply memory array with dynamic selection of the lowest voltage
    16.
    发明专利
    Dual power supply memory array with dynamic selection of the lowest voltage 未知

    公开(公告)号：GB2497180A

    公开(公告)日：2013-06-05

    申请号：GB201220563

    申请日：2012-11-15

    Applicant: IBM

    Inventor： PILO HAROLD ,  BRACERAS GEORGE MARIA ,  PETERSON KIRK DAVID

    IPC: G11C11/412 ,  G11C5/14 ,  G11C7/12 ,  G11C11/417

    Abstract: Disclosed is a memory array (100 figure 1) and associated method in which the lower of two supply voltages Vdd, Vcs from two power supplies is dynamically selected for bitline pre-charge operations. In the memory array, a voltage comparator (160 figure 3) compares the first supply voltage on a first power supply rail Vdd to a second supply voltage Vcs on a second power supply rail and outputs a voltage difference signal 165. If the voltage difference signal has a first value indicating that the first supply voltage is equal to or less than the second supply voltage, then a control circuit 150a ensures that the complementary bitlines 111a 111b connected to a memory cell 110 are pre-charged to the first supply voltage Vdd. If the voltage difference signal has a second value indicating that the first supply voltage is greater than the second supply voltage, then the control circuit ensures that the complementary bitlines are pre-charged to the second supply voltage Vcs. The selection process avoids stability faults due to power supply variation and noise, whilst allowing for reduced power consumption.

    18.
    发明专利
    未知

    公开(公告)号：DE60119995D1

    公开(公告)日：2006-06-29

    申请号：DE60119995

    申请日：2001-12-10

    Applicant: IBM

    Inventor： BARTH E ,  PILO HAROLD

    IPC: G11C7/00 ,  G11C11/407 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4091 ,  G11C11/4094

    Abstract: A system and method is disclosed for writing early within a memory cycle by holding only one of a true bitline and a reference bitline at a fixed potential, e.g. ground, when the sense amplifier is set. The sense amplifier amplifies a small voltage difference between the true bitline and the reference bitline to predetermined high and low voltage logic levels to write a datum to the memory cell. In this way, writing can complete in about the same time as reading, without risking corruption of data on adjacent bitlines in the memory. The bitlines are precharged to a fixed potential in a conduction path through the bitswitches, rather than using local precharge devices at the sense amplifier. To write, bitswitches and write path transistors apply the fixed potential to one of the true bitline and the reference bitline. Bitswitches on such other memory cells not currently being written isolate the bitline pairs coupled to those memory cells when setting the sense amplifiers, such that the stored contents of such memory cells not being written are refreshed (written back) at the time that the selected memory cell is written.

    An efficient semiconductor burn-in circuit and method of operation
    19.
    发明专利
    An efficient semiconductor burn-in circuit and method of operation 未知

    公开(公告)号：SG77705A1

    公开(公告)日：2001-01-16

    申请号：SG1999003828

    申请日：1999-08-05

    Applicant: IBM

    Inventor： BRACERAS GEORGE M ,  COVINO JAMES J ,  HEE RICHARD E ,  PILO HAROLD

    IPC: G11C29/00 ,  G01R31/30 ,  G11B5/187 ,  G06F3/033 ,  G09F9/35 ,  G06F13/00 ,  G11B5/39 ,  G06F12/14

    Abstract: The disclosed invention provides a circuit and burn-in test method for semiconductor devices that increases the speed of burn-in tests. The present invention accomplishes this by causing each of the devices under test to be tested multiple times (from 2 to 32+ times) during each power cycle. By such multiple cycling of the unit under test, during the power cycle, the total test time is shortened. It has also been found that the devices tested in accordance with the present invention are more efficiently stressed and have a reliability greater than devices passing the prior art tests. In accordance with the invention, the memory or logic devices under test are provided with a respective clock means that will operate each of the devices under test through multiple (from 2 to 32+ times) write and read operations during each power cycle. Data coherency for each read operation is provided as is the inversion of data if any fail is recorded during a read operation. Accordingly, the present invention provides a burn-in test that more efficiently stresses semiconductor devices such as memory or logic units, by a factor of up to 32. The invention utilizes the internal clock of a semiconductor device by cycling that clock x times during the period of each external clock cycle in the burn-in test and simultaneously synchronizes these internal cycles with the test cycle, thereby providing coherent data for each internal cycle.

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