公开(公告)号：DE69841981D1

公开(公告)日：2010-12-16

申请号：DE69841981

申请日：1998-09-16

Applicant: IBM

Inventor： GLAISE RENE ,  PORET MICHEL

IPC: H04Q11/04 ,  H04L49/111

公开(公告)号：DE69733741T2

公开(公告)日：2006-04-20

申请号：DE69733741

申请日：1997-08-19

Applicant: IBM

Inventor： BLANC ALAIN ,  ROBBE JEAN-CLAUDE ,  LANDRY CHRISTIAN ,  PORET MICHEL

IPC: H04L12/54 ,  H04L49/111

Abstract: A cell switching module and switching system for routing cells each having a cell header comprising a plurality of input and output ports; at least one common cell storage connected between the input and output ports and comprising a plurality of storage locations having addresses; a storage section for performing storage of cells coming through any one of the input ports into the common cell storage and comprising a plurality of receiver means for performing the physical interface for the plurality of input ports, a plurality of input routers for connection the input ports to the cell storage, a plurality of ASA registers for providing the input routers with addresses to be used for storing the cells into the cell storage; and a retrieve section for retrieving cells from storage and for transporting them to one of the output ports, where the retrieve section comprises a plurality of output routers for retrieving the data stored in any locations of the cell storage, a plurality of drivers for connecting to the output ports, and a plurality of ARA registers for providing addresses of the cells which are to be outputted from the cell storage to the output routers.

公开(公告)号：DE69733741D1

公开(公告)日：2005-08-25

申请号：DE69733741

申请日：1997-08-19

Applicant: IBM

Inventor： BLANC ALAIN ,  ROBBE JEAN-CLAUDE ,  LANDRY CHRISTIAN ,  PORET MICHEL

IPC: H04L12/54 ,  H04L49/111 ,  H04L12/56

Abstract: A cell switching module and switching system for routing cells each having a cell header comprising a plurality of input and output ports; at least one common cell storage connected between the input and output ports and comprising a plurality of storage locations having addresses; a storage section for performing storage of cells coming through any one of the input ports into the common cell storage and comprising a plurality of receiver means for performing the physical interface for the plurality of input ports, a plurality of input routers for connection the input ports to the cell storage, a plurality of ASA registers for providing the input routers with addresses to be used for storing the cells into the cell storage; and a retrieve section for retrieving cells from storage and for transporting them to one of the output ports, where the retrieve section comprises a plurality of output routers for retrieving the data stored in any locations of the cell storage, a plurality of drivers for connecting to the output ports, and a plurality of ARA registers for providing addresses of the cells which are to be outputted from the cell storage to the output routers.

公开(公告)号：DE69809224D1

公开(公告)日：2002-12-12

申请号：DE69809224

申请日：1998-08-28

Applicant: IBM

Inventor： BLANC ALAIN ,  ORENGO GERARD ,  PORET MICHEL

IPC: H03M9/00 ,  H04L49/111 ,  H04Q11/04 ,  H04L12/56

Abstract: A switching apparatus comprising a centralized Switch Core (10) and at least one SCAL element for the attachment of Protocol Adapters. The Switch Core and the SCAL communicate to each other via n parallel serial links with each one transmitting a Logical Unit. Each SCAL comprises both the receive and the transmit part at least one input for receiving cells from said Protocol Adapter; a set of n FIFO queues (21-25) for storing the cells into n parallel busses; and a set of n RAM storages, with each RAM being associated with one Logical Unit. First multiplexing means (31) receive the contents of the parallel busses for performing simultaneously n WRITE operations into the n RAM storages under control of a first set of n tables ( 36-39). Second multiplexing (41) means are provided for making READ operations from said n RAM storages under control of a second set of n tables ( 46-49). By appropriate arrangement of the two sets of tables, which are chosen complementary, the cells which are conveyed through the first multiplexing means, the RAMs and the second multiplexing means are subject to a cell rearrangement enabling to introduce at least one bitmap field, thereby producing said four Logical Units. When two bytes which are processed in parallel have to be loaded at the same time in the same RAM storage (50-80), one particular byte is accidentally stored into one RAM available for a Write operation by means of said first set of tables, thereby causing an alteration to the normal association between said n RAMs and said n Logical Units which is then restablished by said second set of tables.

公开(公告)号：DE3780307T2

公开(公告)日：1993-02-11

申请号：DE3780307

申请日：1987-04-28

Applicant: IBM

Inventor： ROBBE JEAN-CLAUDE ,  MUNIER JEAN-MARIE ,  PORET MICHEL

IPC: G06F13/42

公开(公告)号：DE60317890T2

公开(公告)日：2008-11-27

申请号：DE60317890

申请日：2003-03-31

Applicant: IBM

Inventor： ABEL FRANCOIS G ,  BENNER ALAN ,  BLANC ALAIN ,  COLMANT MICHEL ,  GUSAT MITCH ,  PORET MICHEL ,  SCHUMACHER NORBERT ,  VERHAPPEN MARK

IPC: H04L12/56 ,  H04Q11/04

Abstract: A communication system which consists of several modules—operating in parallel on segments of a packet—to increase speed and handling capacity. One module acts as master, the others are slave modules controlled by control signals derived by the master module. It is important that in each module the data segment and the respective control signal of each packet are correctly synchronized, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.

公开(公告)号：DE60317890D1

公开(公告)日：2008-01-17

申请号：DE60317890

申请日：2003-03-31

Applicant: IBM

Inventor： ABEL FRANCOIS G ,  BENNER ALAN ,  BLANC ALAIN ,  COLMANT MICHEL ,  GUSAT MITCH ,  PORET MICHEL ,  SCHUMACHER NORBERT ,  VERHAPPEN MARK

IPC: H04L12/56 ,  H04Q11/04

Abstract: A communication system which consists of several modules—operating in parallel on segments of a packet—to increase speed and handling capacity. One module acts as master, the others are slave modules controlled by control signals derived by the master module. It is important that in each module the data segment and the respective control signal of each packet are correctly synchronized, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.

公开(公告)号：DE69737676T2

公开(公告)日：2008-01-10

申请号：DE69737676

申请日：1997-08-19

Applicant: IBM

Inventor： BLANC ALAIN ,  SAUREL ALAIN ,  BREZZO BERNARD ,  PORET MICHEL

IPC: H04L49/111 ,  H04Q11/04

Abstract: A switching system comprising a switching structure for routing cells from a set of M input ports towards a set of M output ports. The system includes a set of distributed individual Switch Core Access layer elements which communicate with one input and output port of the switching structure by means of a set of serial communication links. Each SCAL element provides attachment to at least one Protocol Adapter and comprises a set of circuits. The receive part of each circuit, which includes at least one first FIFO storage for storing the cells being received, receives the data cells from the attached Protocol Adapter and introduces at least one extra byte to every cell. Each transmit part of the destination circuit, which includes at least one second FIFO storage having a greater capacity than the first FIFO storage, receives all the cells that are generated at the corresponding output port and uses the at least one extra byte for cell buffering. Additionally, each distrubuted SCAL element comprises control means for performing Time Division Multiplexing access of the FIFOs.

公开(公告)号：AU2003215841A1

公开(公告)日：2003-11-17

申请号：AU2003215841

申请日：2003-03-31

Applicant: IBM

Inventor： ABEL FRANCOIS G ,  BENNER ALAN ,  BLANC ALAIN ,  COLMANT MICHEL ,  GUSAT MITCH ,  PORET MICHEL ,  SCHUMACHER NORBERT ,  VERHAPPEN MARK

IPC: H04L12/56 ,  H04Q11/04

Abstract: A communication system which consists of several modules—operating in parallel on segments of a packet—to increase speed and handling capacity. One module acts as master, the others are slave modules controlled by control signals derived by the master module. It is important that in each module the data segment and the respective control signal of each packet are correctly synchronized, because in large systems the data paths carrying packet segments and the control signal paths may have substantially different delays. The invention provides for measurement of the propagation delay differences and for introducing a controlled delay in each slave module, so that data segments and control signals can be correctly correlated by delaying either the one or the other. Synchronization packets are transmitted besides normal data packets, for obtaining time stamps which are used to determine the delay difference.

公开(公告)号：AT78114T

公开(公告)日：1992-07-15

申请号：AT87430011

申请日：1987-04-22

Applicant: IBM

Inventor： AUSTRUY PIERRE ,  MUNIER JEAN-MARIE ,  PORET MICHEL

IPC: G06F11/16 ,  G06F11/20

Abstract: A Control Unit is described, including a Processing Unit (12) controlled by a Service Processor (14), and a plurality of adapters (18) exchanging data and/or control signals with said Processing Unit (PU). For ensuring a continuous operation of the Control Unit, the adapters are partitioned into at least two sets (56,58), and the PU is partitioned into at least two parts (26,28), each set of adapters being connected to a dedicated PU part by a primary bus (52,54). Besides, in order to allow the fallback of a set of adapters onto another PU part if the PU part to which it is normally connected is inoperative, a bus switching device (30) is provided. This bus switching device includes at least two Switch parts (38,40), and each Switch part performs the switching of a given set of adapters onto a given PU part, according to the status of each PU part. Therefore, each Switch part is connected to a given set of adapters by a primary bus (52,54), and to the other sets of adapters by secondary busses (46,48) which become active in fallback mode.