公开(公告)号：GB2578061B

公开(公告)日：2021-12-01

申请号：GB202000159

申请日：2018-06-07

Applicant: IBM

Inventor： RUQIANG BAO ,  CHOONGHYUN LEE ,  SHOGO MOCHIZUKI ,  CHUN WING YEUNG

IPC: H01L27/04 ,  H01L21/8234 ,  H01L27/088

Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.

公开(公告)号：GB2575933B

公开(公告)日：2021-09-29

申请号：GB201915589

申请日：2018-04-13

Applicant: IBM

Inventor： RUQIANG BAO ,  CHOONGHYUN LEE ,  ZHENG XU ,  ZHENXING BI

IPC: H01L21/8238 ,  H01L21/336 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: Integrated chips include a first semiconductor device and a second semiconductor device. The first semiconductor device includes a semiconductor channel, a first-type work function layer formed from a first material on the semiconductor channel, and a second-type work function layer formed from a second material on the first-type work function later layer. The second semiconductor device includes a semiconductor channel, a second-type work function layer formed the second material on the semiconductor channel, and a thickness matching layer formed on the second-type work function layer of the second semiconductor device, the thickness matching layer having a thickness roughly equal to a thickness of the first-type work function layer.

公开(公告)号：GB2582080A

公开(公告)日：2020-09-09

申请号：GB202007187

申请日：2018-10-12

Applicant: IBM ,  ULVAC INC

Inventor： JOHN ROZEN ,  TAKASHI ANDO ,  VIJAY NARAYANAN ,  RUQIANG BAO ,  YOHEI OGAWA ,  MASANOBU HATANAKA

IPC: H01L21/8238

Abstract: A gate structure for effective work function adjustments of semiconductor devices that includes a gate dielectric on a channel region of a semiconductor device; a first metal nitride in direct contact with the gate dielectric; a conformal carbide of Aluminum material layer having an aluminum content greater than 30 atomic wt. %; and a second metal nitride layer in direct contact with the conformal aluminum (Al) and carbon (C) containing material layer. The conformal carbide of aluminum (Al) layer includes aluminum carbide, or Al4C3, yielding an aluminum (Al) content up to 57 atomic % (at. %) and work function setting from 3.9 eV to 5.0 eV at thicknesses below 2.5 nm. Such structures can present metal gate length scaling and resistance benefit below 25 nm compared to state of the art work function electrodes.

公开(公告)号：GB2575933A

公开(公告)日：2020-01-29

申请号：GB201915589

申请日：2018-04-13

Applicant: IBM

Inventor： RUQIANG BAO ,  CHOONGHYUN LEE ,  ZHENG XU ,  ZHENXING BI

IPC: H01L21/336

Abstract: Semiconductor devices and methods of forming the same include forming vertical semiconductor channels on a bottom source/drain layer in a first-type region and a second-type region. A gate dielectric layer is formed on sidewalls of the vertical semiconductor channels. A first-type work function layer is formed in the first-type region. A second-type work function layer is formed in both the first-type region and the second-type region. A thickness matching layer is formed in the second-type region such that a stack of layers in the first-type region has a same thickness as a stack of layers in the second-type region. Top source/drain regions are formed on a top portion of the vertical channels.

公开(公告)号：GB2575598A

公开(公告)日：2020-01-15

申请号：GB201915742

申请日：2018-04-19

Applicant: IBM

Inventor： SHOGO MOCHIZUKI ,  CHOONGHYUN LEE ,  RUQIANG BAO ,  HEMANTH JAGANNATHAN

IPC: H01L29/78

Abstract: Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are formed by removing portions of the doped sacrificial layers. A bottom contact is formed over the multilayered bottom doped region. The bottom contact includes one or more conductive flanges that fill the cavities.

公开(公告)号：GB2560866A

公开(公告)日：2018-09-26

申请号：GB201812607

申请日：2017-01-06

Applicant: IBM

Inventor： RUQIANG BAO ,  SIDDARTH KRISHNAN ,  UNOH KWON ,  VIJAY NARAYANAN

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method for fabricating a gate stack of a semiconductor device comprising forming a first dielectric layer over a channel region of the device, forming a barrier layer over the first dielectric layer, forming a first gate metal layer over the barrier layer, forming a capping layer over the first gate metal layer, removing portions of the barrier layer, the first gate metal layer, and the capping layer to expose a portion of the first dielectric layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a first nitride layer on exposed portions of the capping layer and the first dielectric layer, depositing a scavenging layer on the first nitride layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.