公开(公告)号：DE3884665T2

公开(公告)日：1994-05-11

申请号：DE3884665

申请日：1988-03-25

Applicant: IBM

Inventor： MONKOWSKI MICHAEL DANIEL ,  SHEPARD JOSEPH FRANCIS

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/60 ,  H01L29/417 ,  H01L29/423 ,  H01L29/732 ,  H01L29/08

Abstract: A novel vertical bipolar device endowed with a lithography-independent tightly controlled sub-micron-wide emitter. In one embodiment, the emitter (114),is contacted by a self-aligned conductive sidewall (112), linked up to a horizontal conductive link (102). The extrinsic base (116, 120), embedded within the collector (14), is recessed below and laterally spaced from the emitter by an insulator layer (118), formed on the emitter sidewall. Transistor action is confined to the small emitter within the intrinsic base, the latter being contiguous with the extrinsic base. The base is contacted by means of a conductive self-aligned silicide (122), formed on the extrinsic base. In a second embodiment, the emitter is of a desired shape with a correspondingly shaped contacting sidewall and pad integral structure. In all embodiments, electrical contact to emitter is established at a distance laterally away from the transistor action area. A novel process of forming vertical (e.g. NPN) bipolar device in which starting with a substrate having an N type epitaxial collector region, a horizontal layer composed of oxide-polysilicon dual layer with a substantially vertical surface is formed. P type intrinsic base precursor is formed in a surface portion of the collector. A submicron-wide sidewall of N doped polysilcon is established on the sidewall. By RIE, a surface portion of the exposed intrinsic base is removed to recess the would-be extrinsic base. An oxide insulator is formed on the sidewall by thermal oxidation and RIE, while simulta- neously driving dopant from the sidewall into the intrinsic base thereunder, thereby forming the emitter with self-aligned polysilicon sidewall contact and delineating the intrinsic base. Extrin-sic base is implanted into the exposed recessed intrinsic base. A self-aligned silicide layer is formed on the extrinsic base as also on the horizon- tal polysilicon layer linked with the sidewall.

公开(公告)号：DE3884665D1

公开(公告)日：1993-11-11

申请号：DE3884665

申请日：1988-03-25

Applicant: IBM

Inventor： MONKOWSKI MICHAEL DANIEL ,  SHEPARD JOSEPH FRANCIS

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/60 ,  H01L29/417 ,  H01L29/423 ,  H01L29/732 ,  H01L29/08

Abstract: A novel vertical bipolar device endowed with a lithography-independent tightly controlled sub-micron-wide emitter. In one embodiment, the emitter (114),is contacted by a self-aligned conductive sidewall (112), linked up to a horizontal conductive link (102). The extrinsic base (116, 120), embedded within the collector (14), is recessed below and laterally spaced from the emitter by an insulator layer (118), formed on the emitter sidewall. Transistor action is confined to the small emitter within the intrinsic base, the latter being contiguous with the extrinsic base. The base is contacted by means of a conductive self-aligned silicide (122), formed on the extrinsic base. In a second embodiment, the emitter is of a desired shape with a correspondingly shaped contacting sidewall and pad integral structure. In all embodiments, electrical contact to emitter is established at a distance laterally away from the transistor action area. A novel process of forming vertical (e.g. NPN) bipolar device in which starting with a substrate having an N type epitaxial collector region, a horizontal layer composed of oxide-polysilicon dual layer with a substantially vertical surface is formed. P type intrinsic base precursor is formed in a surface portion of the collector. A submicron-wide sidewall of N doped polysilcon is established on the sidewall. By RIE, a surface portion of the exposed intrinsic base is removed to recess the would-be extrinsic base. An oxide insulator is formed on the sidewall by thermal oxidation and RIE, while simulta- neously driving dopant from the sidewall into the intrinsic base thereunder, thereby forming the emitter with self-aligned polysilicon sidewall contact and delineating the intrinsic base. Extrin-sic base is implanted into the exposed recessed intrinsic base. A self-aligned silicide layer is formed on the extrinsic base as also on the horizon- tal polysilicon layer linked with the sidewall.

公开(公告)号：DE3474742D1

公开(公告)日：1988-11-24

申请号：DE3474742

申请日：1984-11-06

Applicant: IBM

Inventor： OGURA SEIKI ,  RISEMAN JACOB ,  ROVEDO NIVO ,  SHEPARD JOSEPH FRANCIS

IPC: H01L21/8222 ,  H01L21/28 ,  H01L21/331 ,  H01L21/336 ,  H01L27/06 ,  H01L27/082 ,  H01L29/73 ,  H01L21/60

Abstract: Methods for producing integrated circuit structures are described with reference to a small area lateral bipolar transistor comprising a semiconductor body (10) having surface regions thereof isolated from other such regions by a pattern of dielectric isolation. At least two narrow width PN junction regions are located within at least one of the surface regions. Substantially vertical conformal conductive layers (62, 64) electrically contact each of the PN junction regions which serve as the emitter (56) and collector (58) regions for the bipolar transistor. A junction base region (74) of an opposite conductivity is located between and contiguous to the emitter and the collector junctions. Substantially horizontal conductive layers (22) are in electrical contact with an edge of each of the vertical conductive layers (62, 64) and separated from the surface regions by a first electrically insulating layer (20). A second insulating layer (70) covers the conformal conductive layers. The horizontal conductive layer is patterned so as to form conductive lines electrically separated from one another. A third insulating layer (24) is located over the patterned horizontal conductive layers. An ohmic contact (80, 84) is made to each of the horizontal conductive layers (22) through an opening in the third insulating layer (24) which effectively makes electrical contacts to the emitter (56) and collector (58) regions via the patterned horizontal conductive layers (22) and the vertical conductive layers (62, 64). Another contact (82) is made to the base region (74) which contact is separated from the vertical conductive layers (62, 64) by the second insulating layer (70).

公开(公告)号：AU5884686A

公开(公告)日：1987-05-21

申请号：AU5884686

申请日：1986-06-13

Applicant: IBM

Inventor： COOK ROBERT KIMBAL ,  SHEPARD JOSEPH FRANCIS

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/3065 ,  H05K3/06

Abstract: A method is disclosed for making submicron openings in a substrate. A mesa is formed on the substrate by reactive ion etching techniques. A film is deposited over the entire structure and the mesa is selectively etched away to yield a submicron-sized opening in the film. Using the film as a mask, the substrate exposed thereby is reactively ion etched. An example is given for producing an emitter mask for a polycrystalline silicon base bipolar transistor.

公开(公告)号：DE2967090D1

公开(公告)日：1984-08-09

申请号：DE2967090

申请日：1979-11-19

Applicant: IBM

Inventor： GARDINER JAMES ROBERT ,  PLISKIN WILLIAM AARON ,  REVITZ MARTIN ,  SHEPARD JOSEPH FRANCIS

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L29/417 ,  H01L29/778 ,  H01L21/00

Abstract: A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The instrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing. The yield for the manufacture of devices having thin oxide gates is substantially improved.

公开(公告)号：AU601575B2

公开(公告)日：1990-09-13

申请号：AU1566788

申请日：1988-05-06

Applicant: IBM

Inventor： MONKOWSKI MICHAEL DANIEL ,  SHEPARD JOSEPH FRANCIS

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/60 ,  H01L29/417 ,  H01L29/423 ,  H01L29/732 ,  H01L29/72

Abstract: A novel vertical bipolar device endowed with a lithography-independent tightly controlled sub-micron-wide emitter. In one embodiment, the emitter (114),is contacted by a self-aligned conductive sidewall (112), linked up to a horizontal conductive link (102). The extrinsic base (116, 120), embedded within the collector (14), is recessed below and laterally spaced from the emitter by an insulator layer (118), formed on the emitter sidewall. Transistor action is confined to the small emitter within the intrinsic base, the latter being contiguous with the extrinsic base. The base is contacted by means of a conductive self-aligned silicide (122), formed on the extrinsic base. In a second embodiment, the emitter is of a desired shape with a correspondingly shaped contacting sidewall and pad integral structure. In all embodiments, electrical contact to emitter is established at a distance laterally away from the transistor action area. A novel process of forming vertical (e.g. NPN) bipolar device in which starting with a substrate having an N type epitaxial collector region, a horizontal layer composed of oxide-polysilicon dual layer with a substantially vertical surface is formed. P type intrinsic base precursor is formed in a surface portion of the collector. A submicron-wide sidewall of N doped polysilcon is established on the sidewall. By RIE, a surface portion of the exposed intrinsic base is removed to recess the would-be extrinsic base. An oxide insulator is formed on the sidewall by thermal oxidation and RIE, while simulta- neously driving dopant from the sidewall into the intrinsic base thereunder, thereby forming the emitter with self-aligned polysilicon sidewall contact and delineating the intrinsic base. Extrin-sic base is implanted into the exposed recessed intrinsic base. A self-aligned silicide layer is formed on the extrinsic base as also on the horizon- tal polysilicon layer linked with the sidewall.

公开(公告)号：BR8801815A

公开(公告)日：1988-11-29

申请号：BR8801815

申请日：1988-04-15

Applicant: IBM

Inventor： MONKOWSKI MICHAEL DANIEL ,  SHEPARD JOSEPH FRANCIS

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/60 ,  H01L29/417 ,  H01L29/423 ,  H01L29/732 ,  H01L29/70

Abstract: A novel vertical bipolar device endowed with a lithography-independent tightly controlled sub-micron-wide emitter. In one embodiment, the emitter (114),is contacted by a self-aligned conductive sidewall (112), linked up to a horizontal conductive link (102). The extrinsic base (116, 120), embedded within the collector (14), is recessed below and laterally spaced from the emitter by an insulator layer (118), formed on the emitter sidewall. Transistor action is confined to the small emitter within the intrinsic base, the latter being contiguous with the extrinsic base. The base is contacted by means of a conductive self-aligned silicide (122), formed on the extrinsic base. In a second embodiment, the emitter is of a desired shape with a correspondingly shaped contacting sidewall and pad integral structure. In all embodiments, electrical contact to emitter is established at a distance laterally away from the transistor action area. A novel process of forming vertical (e.g. NPN) bipolar device in which starting with a substrate having an N type epitaxial collector region, a horizontal layer composed of oxide-polysilicon dual layer with a substantially vertical surface is formed. P type intrinsic base precursor is formed in a surface portion of the collector. A submicron-wide sidewall of N doped polysilcon is established on the sidewall. By RIE, a surface portion of the exposed intrinsic base is removed to recess the would-be extrinsic base. An oxide insulator is formed on the sidewall by thermal oxidation and RIE, while simulta- neously driving dopant from the sidewall into the intrinsic base thereunder, thereby forming the emitter with self-aligned polysilicon sidewall contact and delineating the intrinsic base. Extrin-sic base is implanted into the exposed recessed intrinsic base. A self-aligned silicide layer is formed on the extrinsic base as also on the horizon- tal polysilicon layer linked with the sidewall.

公开(公告)号：AU1566788A

公开(公告)日：1988-11-17

申请号：AU1566788

申请日：1988-05-06

Applicant: IBM

Inventor： MONKOWSKI MICHAEL DANIEL ,  SHEPARD JOSEPH FRANCIS

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/60 ,  H01L29/417 ,  H01L29/423 ,  H01L29/732 ,  H01L29/72

Abstract: A novel vertical bipolar device endowed with a lithography-independent tightly controlled sub-micron-wide emitter. In one embodiment, the emitter (114),is contacted by a self-aligned conductive sidewall (112), linked up to a horizontal conductive link (102). The extrinsic base (116, 120), embedded within the collector (14), is recessed below and laterally spaced from the emitter by an insulator layer (118), formed on the emitter sidewall. Transistor action is confined to the small emitter within the intrinsic base, the latter being contiguous with the extrinsic base. The base is contacted by means of a conductive self-aligned silicide (122), formed on the extrinsic base. In a second embodiment, the emitter is of a desired shape with a correspondingly shaped contacting sidewall and pad integral structure. In all embodiments, electrical contact to emitter is established at a distance laterally away from the transistor action area. A novel process of forming vertical (e.g. NPN) bipolar device in which starting with a substrate having an N type epitaxial collector region, a horizontal layer composed of oxide-polysilicon dual layer with a substantially vertical surface is formed. P type intrinsic base precursor is formed in a surface portion of the collector. A submicron-wide sidewall of N doped polysilcon is established on the sidewall. By RIE, a surface portion of the exposed intrinsic base is removed to recess the would-be extrinsic base. An oxide insulator is formed on the sidewall by thermal oxidation and RIE, while simulta- neously driving dopant from the sidewall into the intrinsic base thereunder, thereby forming the emitter with self-aligned polysilicon sidewall contact and delineating the intrinsic base. Extrin-sic base is implanted into the exposed recessed intrinsic base. A self-aligned silicide layer is formed on the extrinsic base as also on the horizon- tal polysilicon layer linked with the sidewall.

公开(公告)号：BR8605249A

公开(公告)日：1987-07-28

申请号：BR8605249

申请日：1986-10-28

Applicant: IBM

Inventor： COOK ROBERTO KIMBALL ,  SHEPARD JOSEPH FRANCIS

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/72

Abstract: A method is disclosed for making submicron openings in a substrate. A mesa is formed on the substrate by reactive ion etching techniques. A film is deposited over the entire structure and the mesa is selectively etched away to yield a submicron-sized opening in the film. Using the film as a mask, the substrate exposed thereby is reactively ion etched. An example is given for producing an emitter mask for a polycrystalline silicon base bipolar transistor.

公开(公告)号：DE3174815D1

公开(公告)日：1986-07-17

申请号：DE3174815

申请日：1981-10-20

Applicant: IBM

Inventor： SHEPARD JOSEPH FRANCIS ,  TSANG PAUL JAMIN

IPC: H01L27/10 ,  H01L21/28 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8242 ,  H01L23/532 ,  H01L27/108 ,  H01L29/78 ,  H01L23/52 ,  G11C11/24