公开(公告)号：DE60224836T2

公开(公告)日：2009-01-08

申请号：DE60224836

申请日：2002-11-07

Applicant: IBM

Inventor： VOLANT RICHARD P ,  BISSON JOHN C ,  COTE DONNA R ,  DALTON TIMOTHY J ,  GROVES ROBERT A ,  PETRARCA KEVIN S ,  STEIN KENNETH J ,  SUBBANNA SESHADRI

IPC: B81C1/00 ,  B81B3/00 ,  H01H49/00 ,  H01H59/00

Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.

公开(公告)号：DE60224836D1

公开(公告)日：2008-03-13

申请号：DE60224836

申请日：2002-11-07

Applicant: IBM

Inventor： VOLANT RICHARD P ,  BISSON JOHN C ,  COTE DONNA R ,  DALTON TIMOTHY J ,  GROVES ROBERT A ,  PETRARCA KEVIN S ,  STEIN KENNETH J ,  SUBBANNA SESHADRI

IPC: B81C1/00 ,  B81B3/00 ,  H01H49/00 ,  H01H59/00

Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.

公开(公告)号：AU2003278176A1

公开(公告)日：2004-05-13

申请号：AU2003278176

申请日：2003-09-18

Applicant: IBM

Inventor： CHINTHAKINDI ANIL K ,  GROVES ROBERT A ,  STEIN KENNETH J ,  SUBBANNA SESHADRI ,  VOLANT RICHARD P

IPC: B81B7/00 ,  B81C1/00 ,  H01G5/011 ,  H01G5/18 ,  H03J3/18 ,  B81B3/00

Abstract: A three-dimensional micro- electromechanical (MEM) varactor is described wherein a movable beam and fixed electrode are respectively fabricated on separate substrates coupled to each other. The movable beam with comb-drive electrodes are fabricated on the "chip side" while the fixed bottom electrode is fabricated on a separated substrate "carrier side". Upon fabrication of the device on both surfaces of the substrate, the chip side device is diced and "flipped over", aligned and joined to the "carrier" substrate to form the final device. Comb-drive (fins) electrodes are used for actuation while the motion of the electrode provides changes in capacitance. Due to the constant driving forces involved, a large capacitance tuning range can be obtained. The three dimensional aspect of the device avails large surface area. When large aspect ratio features are provided, a lower actuation voltage can be used. Upon fabrication, the MEMS device is completely encapsulated, requiring no additional packaging of the device. Further, since alignment and bonding can be done on a wafer scale (wafer scale MEMS packaging), an improved device yield can be obtained at a lower cost.

公开(公告)号：DE60218442T2

公开(公告)日：2007-11-15

申请号：DE60218442

申请日：2002-01-16

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： ARMACOST MICHAEL D ,  AUGUSTIN ANDREAS K ,  FRIESE GERALD R ,  HEIDENREICH JOHN E ,  HUECKEL GARY R ,  STEIN KENNETH J

IPC: H01L21/02 ,  H01L27/04 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522

Abstract: A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 mum) with a bottom etch stop layer, a composite bottom plate having an aluminum layer below a TiN layer, an oxide capacitor dielectric, and a top plate of TiN; in a process that involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.

公开(公告)号：AU2002365158A1

公开(公告)日：2003-07-09

申请号：AU2002365158

申请日：2002-11-07

Applicant: IBM

Inventor： PETRARCA KEVIN S ,  STEIN KENNETH J ,  SUBBANNA SESHADRI ,  VOLANT RICHARD P ,  BISSON JOHN C ,  COTE DONNA R ,  DALTON TIMOTHY J ,  GROVES ROBERT A

IPC: B81B3/00 ,  B81C1/00 ,  H01H49/00 ,  H01H59/00 ,  H01L21/20

Abstract: A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.

公开(公告)号：DE60218442D1

公开(公告)日：2007-04-12

申请号：DE60218442

申请日：2002-01-16

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： ARMACOST MICHAEL D ,  AUGUSTIN ANDREAS K ,  FRIESE GERALD R ,  HEIDENREICH JOHN E ,  HUECKEL GARY R ,  STEIN KENNETH J

IPC: H01L21/02 ,  H01L27/04 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522

Abstract: A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 mum) with a bottom etch stop layer, a composite bottom plate having an aluminum layer below a TiN layer, an oxide capacitor dielectric, and a top plate of TiN; in a process that involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.

公开(公告)号：SG173260A1

公开(公告)日：2011-08-29

申请号：SG2010096741

申请日：2010-12-29

Applicant: CHARTERED SEMICONDUCTOR MFG ,  IBM ,  FREESCALE SEMICONDUCTOR INC ,  INFINEON TECHNOLOGIES CORP ,  FRANCK ARNAUD

Inventor： XIANGDONG CHEN ,  WEIPENG LI ,  MOCUTA ANDA C ,  DAE-GYU PARK ,  SHERONY MELANIE J ,  STEIN KENNETH J ,  HAIZHOU YIN ,  JIN-PING HAN ,  LAEGU KANG ,  MENG LEE YONG ,  WAY TEH YOUNG ,  VOON-YEW THEAN ,  DA ZHANG ,  ARNAUD FRANCK

Abstract: OF THE DISCLOSUREBALANCING NFET AND PFET PERFORMANCE USING STRAINING LAYERSAn integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.Fig. 3

公开(公告)号：CA2708207A1

公开(公告)日：2009-08-20

申请号：CA2708207

申请日：2009-02-11

Applicant: IBM

Inventor： LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K ,  STEIN KENNETH J

IPC: H01L23/48

Abstract: A through substrate (10) via includes an annular conductor layer at a periphery of a through substrate (10) aperture, and a plug layer (24) surrounded by the annular conductor layer. A method for fabricating the through substrate (10) via includes forming a blind aperture within a substrate (10) and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer (20) that does not fill the aperture and plug layer (24) that does fill the aperture. The backside of the substrate (10) may then be planarized to expose at least the planarized conformal conductor layer. (20)

公开(公告)号：AT355614T

公开(公告)日：2006-03-15

申请号：AT02718080

申请日：2002-01-16

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： ARMACOST MICHAEL D ,  AUGUSTIN ANDREAS K ,  FRIESE GERALD R ,  HEIDENREICH JOHN E III ,  HUECKEL GARY R ,  STEIN KENNETH J

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522

Abstract: A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 mum) with a bottom etch stop layer, a composite bottom plate having an aluminum layer below a TiN layer, an oxide capacitor dielectric, and a top plate of TiN; in a process that involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.

公开(公告)号：AU2003278176A8

公开(公告)日：2004-05-13

申请号：AU2003278176

申请日：2003-09-18

Applicant: IBM

Inventor： GROVES ROBERT A ,  VOLANT RICHARD P ,  CHINTHAKINDI ANIL K ,  STEIN KENNETH J ,  SUBBANNA SESHADRI

IPC: B81B7/00 ,  B81C1/00 ,  H01G5/011 ,  H01G5/18 ,  H03J3/18 ,  B81B3/00 ,  H01G5/16

Abstract: A three-dimensional micro- electromechanical (MEM) varactor is described wherein a movable beam and fixed electrode are respectively fabricated on separate substrates coupled to each other. The movable beam with comb-drive electrodes are fabricated on the "chip side" while the fixed bottom electrode is fabricated on a separated substrate "carrier side". Upon fabrication of the device on both surfaces of the substrate, the chip side device is diced and "flipped over", aligned and joined to the "carrier" substrate to form the final device. Comb-drive (fins) electrodes are used for actuation while the motion of the electrode provides changes in capacitance. Due to the constant driving forces involved, a large capacitance tuning range can be obtained. The three dimensional aspect of the device avails large surface area. When large aspect ratio features are provided, a lower actuation voltage can be used. Upon fabrication, the MEMS device is completely encapsulated, requiring no additional packaging of the device. Further, since alignment and bonding can be done on a wafer scale (wafer scale MEMS packaging), an improved device yield can be obtained at a lower cost.