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    12.
    发明专利
    未知

    公开(公告)号：PT94055A

    公开(公告)日：1991-11-29

    申请号：PT9405590

    申请日：1990-05-16

    Applicant: IBM

    Inventor： BAKER ERNEST D ,  DINWIDDIE JOHN M ,  GRICE LONNIE E ,  LOFFREDO JOHN M ,  SANDERSON KENNETH R ,  SUAREZ GUSTAVO A

    IPC: G06F9/46 ,  G06F9/50 ,  G06F11/16 ,  G06F12/02 ,  G06F13/18 ,  G06F15/16 ,  G06F15/167 ,  G06F15/177 ,  G06F

    Abstract: The functions of two virtual operating systems (e.g. S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors dirertly and through the S/88 bus. Each S/370 processor is allocated form 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors across the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs to execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

    SINGLE PHYSICAL MAIN STORAGE SHARED BY TWO OR MORE PROCESSORS EXECUTING RESPECTIVE OPERATING SYSTEMS
    13.
    发明专利
    SINGLE PHYSICAL MAIN STORAGE SHARED BY TWO OR MORE PROCESSORS EXECUTING RESPECTIVE OPERATING SYSTEMS 未知

    公开(公告)号：CA2009548A1

    公开(公告)日：1990-11-17

    申请号：CA2009548

    申请日：1990-02-07

    Applicant: IBM

    Inventor： BAKER ERNEST D ,  DINWIDDIE JOHN M JR ,  GRICE LONNIE E ,  LOFFREDO JOHN M ,  SANDERSON KENNETH R ,  SUAREZ GUSTAVO A

    IPC: G06F9/46 ,  G06F9/50 ,  G06F11/16 ,  G06F12/02 ,  G06F13/18 ,  G06F15/16 ,  G06F15/167 ,  G06F15/177

    Abstract: The functions of two virtual operating systems (e.g. S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors dirertly and through the S/88 bus. Each S/370 processor is allocated form 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors across the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs to execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

    TRUE SINGLE ERROR CORRECTION SYSTEM
    14.
    发明专利
    TRUE SINGLE ERROR CORRECTION SYSTEM 未知

    公开(公告)号：CA1184308A

    公开(公告)日：1985-03-19

    申请号：CA425351

    申请日：1983-04-06

    Applicant: IBM

    Inventor： BANNON ROBERT D ,  BHANSALI MAHENDRA M ,  CHISHOLM DOUGLAS R ,  FINNEY DAMON W ,  MINNICH WALTER D ,  SUAREZ GUSTAVO A

    IPC: G06F11/10 ,  G06F12/16 ,  G06F11/00

    Abstract: TRUE SINGLE ERROR CORRECTION SYSTEM A scheme for true error correction and multiple bit failure detection for a memory system using multiple data bits per chip. An H-Matrix results in syndrome generation of bits that are unique for single bit failures that will not match syndromes generated by multiple bit failures. All multiple bit failures are detected without miscorrecting any single bits that have not failed. Single pass logic employs all syndromes in parallel inputs to determine the presence of a single bit failure for subsequent correction and also detects the presence of multiple bit failures.

    15.
    发明专利
    未知

    公开(公告)号：BR9200321A

    公开(公告)日：1992-10-13

    申请号：BR9200321

    申请日：1992-01-31

    Applicant: IBM

    Inventor： DINWIDDIE JOHN M JR ,  FREEMAN BOBBY J ,  MICALLEF THOMAS J ,  SUAREZ GUSTAVO A ,  WILKIE BRUCE J

    IPC: G09G5/00 ,  G06F3/14 ,  G06T3/00 ,  G09G5/14 ,  H04N5/765 ,  G06F15/62 ,  G06K9/36

    Abstract: A multimedia solution is presented which allows a multimedia architecture to be implemented on an existing computer system. According to the invention, an expansion unit which incorporates a multimedia architecture is provided. The expansion unit is connected to an existing computer system via an expansion slot of an I/O bus of the existing computer as well as via a display device output terminal of the computer. The expansion unit is also connected to a display device. Accordingly, the expansion unit controls the presentation which is provided on the display device.

    16.
    发明专利
    未知

    公开(公告)号：BR9105310A

    公开(公告)日：1992-09-29

    申请号：BR9105310

    申请日：1991-12-10

    Applicant: IBM

    Inventor： DINWIDDIE JOHN M JR ,  FREEMAN BOBBY J ,  SUAREZ GUSTAVO A ,  WILKIE BRUCE J

    IPC: G06F3/048 ,  G06F3/14 ,  G09G1/16 ,  G09G5/00 ,  G06F13/00

    Abstract: An information handling apparatus for transferring and composing image signals for display including a bus interface circuit adapted to allow selective access to a bus of an independent image signal generated by an independent image source. The selective access enables composition of the independent image signal in response to control information; the composition enables real time display of a composed image signal.

    19.
    发明专利
    未知

    公开(公告)号：BR9002303A

    公开(公告)日：1991-07-30

    申请号：BR9002303

    申请日：1990-05-17

    Applicant: IBM

    Inventor： FREEMAN BOBBY J ,  DINWIDDIE JOHN M JR ,  GRICE LONNIE E ,  LOFFREDO JOHN M ,  SANDERSON KENNETH R ,  SUAREZ GUSTAVO A

    IPC: G06F15/16 ,  G06F9/46 ,  G06F11/16 ,  G06F15/177 ,  H04L29/00

    Abstract: The functions of two virtual operating systems (e.g. S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated form 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors across the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs to execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

    FAULT TOLERANT DATA PROCESSING SYSTEM
    20.
    发明专利
    FAULT TOLERANT DATA PROCESSING SYSTEM 未知

    公开(公告)号：CA2009765A1

    公开(公告)日：1990-11-17

    申请号：CA2009765

    申请日：1990-02-07

    Applicant: IBM

    Inventor： BAKER ERNEST D ,  DINWIDDIE JOHN M JR ,  GRICE LONNIE E ,  JOYCE JAMES M ,  LOFFREDO JOHN M ,  SANDERSON KENNETH R ,  SUAREZ GUSTAVO A

    IPC: G06F11/18 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177

    Abstract: The functions of two virtual operating systems (e.g. S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated form 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors across the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs to execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

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