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公开(公告)号：FR2356148A1
公开(公告)日：1978-01-20
申请号：FR7714014
申请日：1977-05-03
Applicant: IBM
Inventor： HELLER LAWRENCE G , TERMAN LEWIS M , YEE YEN S
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12.发明专利
公开(公告)号：FR2316800A1
公开(公告)日：1977-01-28
申请号：FR7615576
申请日：1976-05-17
Applicant: IBM
Inventor： SPAMPINATO DOMINIC P , TERMAN LEWIS M
IPC: G11C11/401 , G05F3/20 , G11C11/35 , G11C19/28 , H01L21/822 , H01L27/04 , H01L29/768 , H03K19/096 , H03K17/30 , H01L29/78
Abstract: A method of generating a biassing voltage for an FET switching circuit integrated in a chip, employs charge injection into the substrate. A first doped zone of conduction type opposite so that of the substrate and at least two insulated electrodes are on the substrate. The substrate is floating, while the doped zone is at a fixed potential and the two electrodes are connected to pulse voltage sources, so that the aimed at threshold voltage is applied to one electrode, and a higher voltage to the other. The difference between the aimed at and actual voltage, injects the charges into the substrate. The first electrode is located between the doped zone and the second electrode. A second doped zone of opposite conductivity type is located in the substrate underneath the second electrode.
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公开(公告)号：CA1097810A
公开(公告)日：1981-03-17
申请号：CA272815
申请日：1977-02-28
Applicant: IBM
Inventor： HELLER LAWRENCE G , TERMAN LEWIS M
IPC: H03M1/44 , G11C11/56 , G11C19/18 , G11C19/36 , G11C27/02 , H03K4/02 , H03M1/00 , H03M1/66 , G11C11/40
Abstract: CHARGE-TRANSFER BINARY SEARCH GENERATING CIRCUIT A bucket brigade circuit is described for generating a sequence of packets of charge carriers of the form QR/2, QR/4, QR/8....QR/2N where N is an integer. The charge packets thus generated can be employed in combinations in either digital-to-analog or analog-to-digital converters. The charge generation circuit requires two equal capacitors which are used for charge redistribution. To obtain accurate quantities of charge in the generated charge packets the capacitors employed should be large, however the use of large capacitors results in low operating speed because of the large charge transfer time constants involved. The described circuit provides a scheme to reduce charge transfer time constants and therefore obtain greater speed while still permitting the use of large capacitors for high accuracy. The circuit includes a small coupling capacitor connected in series with one of the charge redistribution capacitors to produce a total capacitance which is equal to or smaller than the coupling capacitance. The sequence of charge carriers produced by the circuit can be injected into either a bucket brigade circuit or a charge-coupled-device circuit for use, for example, in digital-to-analog and analog-to-digital converters.
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公开(公告)号：CA1072644A
公开(公告)日：1980-02-26
申请号：CA278859
申请日：1977-05-20
Applicant: IBM
Inventor： HELLER LAWRENCE G , TERMAN LEWIS M , YEE YEN S
Abstract: HIGH ACCURACY MOS COMPARATOR The voltages to be compared are applied to a passive MOS capacitor differencing circuit for producing a voltage difference signal, which then is amplified by a high-gain non-precision FET amplifier, the output of which is passed through a low output impedance FET buffer amplifier to an FET latching circuit. Capacitive coupling is used for enabling the amplifiers to be independently biased and to eliminate D.C. offsets. The operating cycle of the comparator has two periods. During an initial set-up or preconditioning period the amplifiers are self-biased by appropriate switching actions which cause each of the amplifiers to be set at a desired operating point that is maintained when its respective bias switching connection subsequently is opened. The bias switch openings in the respective amplifier and latching stages are timed to occur in a chosen sequence which causes the switching transients to be absorbed. At the end of the preconditioning period, the comparator is set up for operation in the comparison period during which the input signals are compared.
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公开(公告)号：FR2345788A1
公开(公告)日：1977-10-21
申请号：FR7703515
申请日：1977-02-01
Applicant: IBM
Inventor： HELLER LAWRENCE G , TERMAN LEWIS M
IPC: H03M1/44 , G11C11/56 , G11C19/18 , G11C19/36 , G11C27/02 , H03K4/02 , H03M1/00 , H03M1/66 , G11C19/28 , H03K13/02
Abstract: A bucket brigade circuit is described for generating a sequence of packets of charge carriers of the form QR/2, QR/4, QR/8....QR/2N where N is an integer. The charge packets thus generated can be employed in combinations in either digital-to-analog or analog-to-digital converters. The charge generation circuit requires two equal capacitors which are used for charge redistribution. To obtain accurate quantities of charge in the generated charge packets the capacitors employed should be large, however the use of large capacitors results in low operating speed because of the large charge transfer time constants involved. The described circuit provides a scheme to reduce charge transfer time constants and therefore obtain greater speed while still permitting the use of large capacitors for high accuracy. The circuit includes a small coupling capacitor connected in series with one of the charge redistribution capacitors to produce a total capacitance which is equal to or smaller than the coupling capacitance. The sequence of charge carriers produced by the circuit can be injected into either a bucket brigade circuit or a charge-coupled-device circuit for use, for example, in digital-to-analog and analog-to-digital converters.
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Patent Agency Ranking
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公开(公告)号：CA895039A
公开(公告)日：1972-03-07
申请号：CA895039D
Applicant: IBM
Inventor： PLESHKO PETER , TERMAN LEWIS M
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公开(公告)号：CA1228425A
公开(公告)日：1987-10-20
申请号：CA478628
申请日：1985-04-09
Applicant: IBM
Inventor： LU NICKY C , NING TAK H , TERMAN LEWIS M
IPC: H01L27/10 , G11C11/34 , G11C11/40 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
Abstract: DYNAMIC RAM CELL WITH MOS TRENCH CAPACITOR IN CMOS This invention relates generally to Dynamic Random Access Memory (DRAM) cells and more particularly relates to a DRAM cell wherein the storage capacitor of the cell is disposed in a trench formed in a semiconductor substrate. Still more particularly, it relates to a DRAM cell wherein at least a portion of the substrate is heavily doped and forms the counterelectrode of the storage capacitor while a heavily doped polycrystalline plug disposed in the trench capacitor forms the other electrode of the storage capacitor. The DRAM cell includes a field effect access transistor disposed in a well which is opposite in conductivity type to that of the substrate. The well itself is formed in a lightly doped portion of the substrate and may be n or p-type conductivity with the other portions of the cell having conductivity types appropriate for devices fabricated in the CMOS environment. The trench capacitor extends from the surface of the well through the well and lightly doped substrate portion into the heavily doped portion of the substrate. The electrode disposed in the trench is directly connected to the source/drain of the access transistor.
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公开(公告)号：CA1223352A
公开(公告)日：1987-06-23
申请号：CA485187
申请日：1985-06-25
Applicant: IBM
IPC: H03K19/096 , G11C8/10 , G11C11/34 , G11C11/407 , G11C11/413 , G06F12/02 , G11C7/00
Abstract: HIGH-PERFORMANCE, HIGH-DENSITY CMOS DECODER/DRIVER CIRCUIT A decoder/driver circuit for a semiconductor memory having A1 to AN (true) and ?? to ?? (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A .PHI.PC line is included for receiving a .PHI.PC precharge clock signal thereon and a .PHI.R line is provided for receiving a .PHI.R reset clock signal thereon. The decoder/driver circuit includes a NOR decoder means having a plurality of transistor switching devices connected to A1 to AN-1 of ?? to ???? of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on a decoder output node depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices connected to the output node of the decoder to produce a first selection signal when the decoder output node and the AN line is high and a second selection signal when the decoder output node and the ?? line is high. A driver circuit is connected to the selection means and is responsive to the output signal of the NOR decoder circuit and the first selection signal to provide an output signal on a first memory word line and is further responsive to the output signal of the NOR decoder circuit and the second selection signal to provide an output signal on a second memory word line.
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20.发明专利
公开(公告)号：CA1100638A
公开(公告)日：1981-05-05
申请号：CA272261
申请日：1977-02-21
Applicant: IBM
Inventor： HELLER LAWRENCE G , TERMAN LEWIS M
IPC: H03M1/44 , H01L29/768 , H01L29/78 , H03M1/00 , H03K13/03
Abstract: ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTER CIRCUITS EMPLOYING CHARGE REDISTRIBUTION Analog-to-digital (A/D) and digital-to-analog (D/A) converter circuits are provided using charge redistribution. The analog-to-digital converter circuit also employs successive approximation binary search techniques wherein the number of search voltages generated is a minimum. The analog-to-digital circuit includes a digital-to-analog converter circuit, a comparator circuit and a logic control means. The digital-to-analog circuit, under control of the logic means, accepts a reference voltage input and produces a sequence of search voltages which are compared with an unknown analog input voltage at the comparator. The resultant outputs from the comparator are applied to the control logic to determine the search voltage sequence. The digital-to-analog converter for the aforesaid circuit is provided in one embodiment employing charge-coupled-device technology. A substrate and two storage electrodes are combined to produce two potential storage wells and a transfer electrode is provided to move charge carriers between the storage wells. A reference charge packet QR is stored and divided by charge redistribution between the two potential wells to produce a sequence of charge packets of value QR/2, QR/4, QR/8, QR/16 etc. which can be selectively combined to produce analog output of a D/A converter. In the A/D converter the same sequence of charge packets is used to generate the equivalent of a binary search sequence QR/2, QR?QR/4, ?QR/8 etc. In another embodiment a bucket brigade device is provided to accomplish the same result. Because of the technique of charge redistribution wherein precise amounts of charge can be shifted in either direction between storage means, the total number of search value steps is a minimum. YO975-017 -1-
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