公开(公告)号：JPH11353267A

公开(公告)日：1999-12-24

申请号：JP11012299

申请日：1999-04-16

Applicant: IBM

Inventor： KELLEY RICHARD ALLEN ,  DANNY MARVIN NEIL ,  THURBER STEVEN MARK

IPC: G06F13/10 ,  G06F9/445 ,  G06F13/14

Abstract: PROBLEM TO BE SOLVED: To provide an improved computer system having an extension bus which can add a peripheral device to the system. SOLUTION: In a method registering newly added peripheral device to a computer system 100, the peripheral device has a response by transmitting a state message to a bus of the system 100 within a prescribed period after the asserting of a reset signal supplied to the peripheral device is released and in response to the access trial given to the peripheral device. Thus, it's possible to evade the stoppage of a function and also to evade the necessity to reboot of the system 100 to initialize a new peripheral device to the system 100. If a a response is generated within an initialization waiting time period shorter than the prescribed period, the peripheral device is allowed to transmit a trial response in an early stage. Furthermore, the peripheral device can respond to a non-configuration cycle right after a configuration is completed. The internal logic of the peripheral device is initialized after responded by a state message.

公开(公告)号：JPH11353244A

公开(公告)日：1999-12-24

申请号：JP11065099

申请日：1999-04-19

Applicant: IBM

Inventor： BOSSEN DOUGLAS CRAIG ,  MCLAUGHLIN CHARLES ANDREW ,  DANNY MARVIN NEIL ,  NICHOLSON JAMES OTTO ,  THURBER STEVEN MARK

IPC: G06F13/00 ,  G06F11/07

Abstract: PROBLEM TO BE SOLVED: To prevent damage due to a bus error in loading operation or storing operation through the identification of a device which encountered an error before by using forcible illegal data parity or 0-byte enabling. SOLUTION: Device select lines from respective I/O devices 132 and 134 are connected individually to a PCT host bridge 124 and if an error occurs on a PCI(peripheral component interconnect) bus, the device number of the faulty device is recorded in an error register 204. Following loading operation and storing operation are suspended until the error register is reset and until the device number of the object device is checked in the error register. If the object device got out of order before, the completion of the loading/storing operation on the device is stopped by forcing the illegal parity or setting all of byte enabling to zero. The I/O devices activate their device select lines when the illegal parity of 0-byte enabling is forced to answer a load request or store request, but accept no store data.

公开(公告)号：JP2009123217A

公开(公告)日：2009-06-04

申请号：JP2008291371

申请日：2008-11-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BROWN AARON CHES ,  RENATO J RECIO ,  THURBER STEVEN MARK ,  DOUGLAS M FREIMUTH ,  JAMES A PAFUMI

IPC: G06F13/14 ,  G06F9/46 ,  G06F13/10

CPC classification number: G06F13/385 ,  G06F9/45558 ,  G06F2009/45579 ,  G06F2213/0026

Abstract: PROBLEM TO BE SOLVED: To provide a system and a method for directly assigning virtual functions (VFs) to client partitions for normal input/output operations by providing a mechanism for an input-output virtualization management partition (IMP) to control the shared functionality of an input/output virtualization (IOV) correspondence input/output adapter through a physical function (PF) of the IOA. SOLUTION: A hypervisor provides device-independent facilities to the code running in the IMP and client partitions. The IMP may include a device specific code without the hypervisor needing to sacrifice its size, robustness, and upgradeability. The hypervisor provides the virtual intermediary functionally for the sharing and control of the IOA's control functions. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于通过为输入 - 输出虚拟化管理分区（IMP）提供机制来为正常输入/输出操作直接分配虚拟功能（VF）到客户机分区的系统和方法，以控制 通过IOA的物理功能（PF），输入/输出虚拟化（IOV）对应输入/输出适配器的共享功能。 解决方案：管理程序为IMP和客户端分区中运行的代码提供与设备无关的功能。 IMP可以包括不需要管理程序的设备特定代码来牺牲其大小，鲁棒性和可升级性。 管理程序为虚拟中介功能提供了IOA控制功能的共享和控制功能。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008171413A

公开(公告)日：2008-07-24

申请号：JP2007324521

申请日：2007-12-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RENATO J RECIO ,  THURBER STEVEN MARK ,  FREIMUTH DOUGLAS M ,  SALZBERG CLAUDIA ANDREA ,  VARGAS JACOBO A

IPC: G06F15/17 ,  G06F13/38

CPC classification number: G06F13/28

Abstract: PROBLEM TO BE SOLVED: To provide a system and method for communication between host systems using socket connection and shared memories. SOLUTION: In the socket-based communication, a work queue in host systems can be used to listen for an incoming socket initialization request. As shown in Fig. 10, a first host system 1010 wishing to establish socket communication connection with a second host system 1020 can generate a socket initialization request work queue element in its work queue and can inform the second host system 1020 that the socket initialization request work queue element is available for processing. Then, the second host system can accept or deny the request. When the second host system accepts the request, the second host system returns a second half of a socket parameter for use by the first host system in performing socket based communications between the first and second host systems. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种使用插座连接和共享存储器的主机系统之间的通信的系统和方法。 解决方案：在基于套接字的通信中，主机系统中的工作队列可用于监听传入套接字初始化请求。 如图所示。 如图10所示，希望与第二主机系统1020建立套接字通信连接的第一主机系统1010可以在其工作队列中生成套接字初始化请求工作队列元素，并且可以通知第二主机系统1020套接字初始化请求工作队列元素是可用的 用于处理。 然后，第二个主机系统可以接受或拒绝该请求。 当第二主机系统接受请求时，第二主机系统返回套接字参数的后半部分供第一主机系统在第一和第二主机系统之间执行基于套接字的通信时使用。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008152786A

公开(公告)日：2008-07-03

申请号：JP2007324603

申请日：2007-12-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SALZBERG CLAUDIA ANDREA ,  RENATO J RECIO ,  THURBER STEVEN MARK ,  FREIMUTH DOUGLAS M ,  VARGAS JACOBO A

IPC: G06F13/14 ,  G06F13/10

CPC classification number: G06F9/4856

Abstract: PROBLEM TO BE SOLVED: To provide a system and a method for migration of single route stateless virtual function. SOLUTION: A Single-Root PCI Configuration Manager (SR-PCIM) provides a system image (SI) with possible virtual function (VF) migration scenarios supported by the endpoint (EP). The SR-PCIM may be instructed that a stateless migration of a VF and its associated application(s) from one SI to another is required. Outstanding requests to the VF are completed and any applications associated with the VF are removed from the SI and the VF is detached from its associated physical function (PF). The SWI may then attach the VF to a target PF which may be in the same or a different EP. The SWI makes the VF available to the SI with which the VF is now associated and the SI configures the VF thereby making it available for use by associated applications. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供用于单路无状态虚拟功能迁移的系统和方法。 解决方案：单根PCI配置管理器（SR-PCIM）提供了一个系统映像（SI），具有由端点（EP）支持的可能的虚拟功能（VF）迁移方案。 可以指示SR-PCIM需要将VF及其相关联的应用程序从一个SI到另一个SI的无状态迁移。 完成对VF的未完成请求，并将与VF关联的所有应用程序从SI中删除，并且VF与其关联的物理功能（PF）分离。 然后，SWI可以将VF附接到可以在相同或不同EP中的目标PF。 SWI使VF可用于现在与VF关联的SI，SI配置VF，从而使其可供相关应用使用。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008102930A

公开(公告)日：2008-05-01

申请号：JP2007267625

申请日：2007-10-15

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SALZBERG CLAUDIA ANDREA ,  RENATO J RECIO ,  THURBER STEVEN MARK ,  MOHRTUL DANIEL FRANK

IPC: G06F13/12 ,  G06F3/06 ,  G06F12/10

CPC classification number: G06F12/1081 ,  G06F12/1475 ,  G06F13/122 ,  G06F2212/683

Abstract: PROBLEM TO BE SOLVED: To provide an apparatus and method for communicating with an input/output (I/O) adapter configured to communicate with a locally attached I/O device using cached address translation. SOLUTION: With the apparatus and method, in response to receiving a storage transaction request, a queue element is created in a command queue specifying an untranslated buffer address. The queue element may be retrieved by the I/O adapter and a determination may be made as to whether the queue element contains a read operation command. If so, a translation request may be sent from the I/O adapter to a root complex at substantially a same time as the read operation command is sent to a locally attached external I/O device. The translated address corresponding to the untranslated address of the queue element may be returned and stored in the I/O adapter prior to receiving the data read from the external I/O device. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于与配置为使用高速缓存的地址转换与本地连接的I / O设备进行通信的输入/输出（I / O）适配器通信的装置和方法。 解决方案：利用设备和方法，响应于接收到存储事务请求，在指定非翻译缓冲器地址的命令队列中创建队列元素。 可以由I / O适配器检索队列元素，并且可以确定队列元素是否包含读操作命令。 如果是这样，则可以在将读取操作命令发送到本地连接的外部I / O设备的同时将翻译请求从I / O适配器发送到根复合体。 在接收到从外部I / O设备读取的数据之前，可以将对应于队列元素的未翻译地址的转换地址返回并存储在I / O适配器中。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：DE69419680D1

公开(公告)日：1999-09-02

申请号：DE69419680

申请日：1994-09-15

Applicant: IBM

Inventor： ARNDT RICHARD LOUIS ,  NICHOLSON JAMES OTTO ,  SILHA EDWARD JOHN ,  THURBER STEVEN MARK ,  YOUNGS AMY MAY

IPC: G06F15/16 ,  G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F15/177 ,  G06F13/26

Abstract: An interrupt subsystem within a data processing system is scalable from low-end uniprocessor systems to high-end multi-processor (MP) systems. This interrupt subsystem provides for queuing of interrupts from many sources, and for queuing of interrupts to the best processor in a multi-processor system. The external interrupt mechanism is separated into two layers, an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service/process the interrupt. By providing two layers within the interrupt subsystem, application or system software can be written which is independent from the types or sources of interrupts. The interrupt routing layer hides the details of a particular hardware implementation from the software. The interrupt presentation layer interfaces to the system and/or application software, and provides hardware independent functionality.

公开(公告)号：BR9403514A

公开(公告)日：1995-06-20

申请号：BR9403514

申请日：1994-09-12

Applicant: IBM

Inventor： ARNDT RICHARD LOUIS ,  NICHOLSON JAMES OTTO ,  SILHA EDWARD JOHN ,  THURBER STEVEN MARK ,  YOUNDS AMY MAY

IPC: G06F15/16 ,  G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F15/177 ,  G06F13/20

Abstract: An interrupt subsystem within a data processing system is scalable from low-end uniprocessor systems to high-end multi-processor (MP) systems. This interrupt subsystem provides for queuing of interrupts from many sources, and for queuing of interrupts to the best processor in a multi-processor system. The external interrupt mechanism is separated into two layers, an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service/process the interrupt. By providing two layers within the interrupt subsystem, application or system software can be written which is independent from the types or sources of interrupts. The interrupt routing layer hides the details of a particular hardware implementation from the software. The interrupt presentation layer interfaces to the system and/or application software, and provides hardware independent functionality.

公开(公告)号：DE602007009835D1

公开(公告)日：2010-11-25

申请号：DE602007009835

申请日：2007-05-23

Applicant: IBM

Inventor： BENDER CARL ALFRED ,  BUCKLAND PATRICK ALLEN ,  THURBER STEVEN MARK ,  YANES ADALBERTO GUILLERMO

IPC: G06F12/02 ,  G06F13/28

公开(公告)号：DE69914966D1

公开(公告)日：2004-04-01

申请号：DE69914966

申请日：1999-04-19

Applicant: IBM

Inventor： BOSSEN DOUGLAS CRAIG ,  MCLAUGHLIN CHARLES ANDREW ,  NEAL DANNY MARVIN ,  NICHOLSON JAMES OTTO ,  THURBER STEVEN MARK

IPC: G06F13/00 ,  G06F11/07 ,  G06F11/00

Abstract: Device selects lines 202n from each I/O device 132 are brought into a PCI host bridge 124 individually so that the device number of a failing device may be logged in an error register 204 when an error is seen on the PCI bus. Until the error register is reset, subsequent load and store operations are delayed until the device number of the subject device may be checked against the error register. If the subject device is a previously failing device, the load/store operation to that device is prevented from completing, either by forcing bad parity or zeroing all byte enables. By forcing bad parity or zero byte enables, the I/O device will respond to the load or store request by activating its device select line, but will not accept store data. Operations to devices which are not logged in the error register are permitted to proceed normally, as are all load store operations when the error register is clear. Normal system operations are thus not impacted, and operations during error recovery are permitted to proceed if no further damage will be caused by such operations.