公开(公告)号：DE102008064719B4

公开(公告)日：2018-06-07

申请号：DE102008064719

申请日：2008-05-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GILES LUIS-FELIPE ,  GOLDBACH MATTHIAS ,  BARTELS MARTIN ,  KUPPER PAUL

IPC: H01L21/22 ,  H01L21/24 ,  H01L21/265 ,  H01L21/328 ,  H01L21/74

Abstract: Verfahren zum Herstellen einer integrierten Schaltung, wobei das Verfahren folgende Schritte aufweist:Bilden (100) einer Mehrzahl von Mikrohohlräumen in einem Substrat mittels eines Implantierens von H-, He-, F-, Ne-, Cl- oder Ar-Ionen in das Substrat;Erzeugen (105) einer Amorphisierung des Substrats durch Implantation von Germaniumionen und/oder Siliziumionen, wobei kristallographische Defekte gebildet werden,Dotieren des Substrats mit Dotierungsatomen; undAusheilen (115) des Substrats bei einer Temperatur von weniger als 580°C, so dass zumindest ein Teil der kristallographischen Defekte unter Verwendung der Mikrohohlräume beseitigt wird;wobei ein Halbleiterelement unter Verwendung der Dotierungsatome gebildet wird.

公开(公告)号：DE102008022502B4

公开(公告)日：2018-06-07

申请号：DE102008022502

申请日：2008-05-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GILES LUIS-FELIPE ,  GOLDBACH MATTHIAS ,  BARTELS MARTIN ,  KÜPPER PAUL

IPC: H01L21/22 ,  H01L21/24 ,  H01L21/265 ,  H01L21/328 ,  H01L21/74

Abstract: Verfahren zum Herstellen einer integrierten Schaltung, wobei das Verfahren folgende Schritte aufweist:Bilden einer Mehrzahl von Mikrohohlräumen in einem Substrat, was ein Implantieren von H-, He-, F-, Ne-, Cl- oder Ar-Ionen aufweist;Erzeugen einer Amorphisierung des Substrats durch Implantation von Germaniumionen und/oder Siliziumionen, wobei kristallographische Defekte gebildet werden;Dotieren des Substrats mit Dotierungsatomen;Aufbringen einer amorphen Schicht aus Silizium über dem Substrat; undAusheilen des Substrats bei einer Temperatur von weniger als 650°C, so dass zumindest ein Teil der kristallographischen Defekte unter Verwendung der Mikrohohlräume beseitigt wird;wobei ein Halbleiterelement unter Verwendung der Dotierungsatome gebildet wird.

公开(公告)号：DE102008022502A1

公开(公告)日：2008-11-20

申请号：DE102008022502

申请日：2008-05-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GILES LUIS-FELIPE ,  GOLDBACH MATTHIAS ,  BARTELS MARTIN ,  KUEPPER PAUL

IPC: H01L21/22 ,  H01L21/24 ,  H01L21/265 ,  H01L21/328 ,  H01L21/74

Abstract: A method of producing a semiconductor element in a substrate includes forming a plurality of micro-cavities in a substrate, creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms, depositing an amorphous layer on top of the substrate, and annealing the substrate, such that at least a part of the crystallographic defects is eliminated using the micro-cavities. The semiconductor element is formed using the doping atoms.

公开(公告)号：DE10055712B4

公开(公告)日：2006-07-13

申请号：DE10055712

申请日：2000-11-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  GOLDBACH MATTHIAS ,  SCHUMANN DIRK

IPC: H01L21/8242 ,  C25F3/12 ,  H01L21/3063 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L29/92

Abstract: An electrochemical method is provided for producing trenches for trench capacitors in p-doped silicon with a very high diameter/depth aspect ratio for large scale integrated semiconductor memories. Trenches (macropores) having a diameter of less than about 100 nm and a depth of more than 10 mum can be produced on p-doped silicon having a very low resistivity at a high etching rate.

公开(公告)号：DE10147120B4

公开(公告)日：2005-08-25

申请号：DE10147120

申请日：2001-09-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  GOLDBACH MATTHIAS ,  LUETZEN JOERN ,  HECHT THOMAS

IPC: H01L21/8242 ,  H01L27/108

Abstract: A trench capacitor has a first capacitor electrode, a second capacitor electrode, and a dielectric, which is arranged between the capacitor electrodes. The first capacitor electrode has a tube-like structure, which extends into a substrate. The second capacitor electrode includes a first section which is opposite to the internal side of the tube-like structure, with the dielectric arranged therebetween, and a second section, which is opposite to the external side of the tube-like structure with the dielectric arranged therebetween.

公开(公告)号：DE10358599B3

公开(公告)日：2005-06-23

申请号：DE10358599

申请日：2003-12-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHOLZ ARND ,  GOLDBACH MATTHIAS

IPC: H01L21/8242

Abstract: A trench (2) is formed in the substrate (1). Its wall (21) is formed by a first collar (41) in the lower trench section (2'). In the central- and upper trench sections (2'', 2''') it is formed by the substrate. The trench is provided with a capacitor dielectric (51). A lower region (2'-A) of the lower trench zone is provided with a first filling (61). The trench wall above this first filling, including the central trench section, is provided with a second collar (42). The trench is filled with a second filling (62) above the first, including the central trench section. A trench (2) is formed in the substrate (1). Its wall (21) is formed by a first collar (41) in the lower trench section (2'). In the central- and upper trench sections (2'', 2''') it is formed by the substrate. The trench is provided with a capacitor dielectric (51). A lower region (2'-A) of the lower trench zone is provided with a first filling (61). The trench wall above this first filling, including the central trench section, is provided with a second collar (42). The trench is filled with a second filling above the first, including the central trench section. A second vertical part of the trench (23) is covered with a self-adjusting mask, with a first vertical part (22) of the trench remaining uncovered. The second collar in the first vertical partial trench (22) is removed. The self-adjusting mask and second filling are removed. The bare capacitor dielectric in the first vertical partial trench is removed. The trench is filled with a contacting filling to form a trenched contact between substrate (1) and first filling, through the contacting filling.

公开(公告)号：DE10351030A1

公开(公告)日：2005-06-09

申请号：DE10351030

申请日：2003-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  FREY ULRICH ,  FISCHER BJOERN

IPC: H01L21/336 ,  H01L21/8242 ,  H01L29/423 ,  H01L29/78 ,  H01L27/108 ,  G11C11/40

Abstract: Transistor structures, with one source/drain region connected to a charge storage device to be insulated includes an asymmetric gate conductor structure. At a first side wall, which faces the one source/drain region, the asymmetric gate conductor structure has a side wall oxide with a greater thickness and a bird's beak structure with a greater length than at an opposite, second side wall. An effective channel length is increased for the same feature size of the gate conductor structure. Memory cells can be realized in a higher density.

公开(公告)号：DE10234735A1

公开(公告)日：2004-02-12

申请号：DE10234735

申请日：2002-07-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HECHT THOMAS ,  GOLDBACH MATTHIAS ,  SCHROEDER UWE

IPC: C23C16/04 ,  C23C16/44 ,  C23C16/455 ,  H01L21/285 ,  H01L21/3065 ,  H01L21/314 ,  H01L21/334 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: Structurization of process area (2) of substrate (1) with relief, inclined and/or perpendicular to horizontal substrate surface (101) and extending into relief to given coating depth (102) between relief depth (103) and substrate surface, involves depositing liner (3) from precursors in process chamber; limited deposition of at least one precursor and coating in uniform thickness almost only on upper part between substrate surface and coating depth.

公开(公告)号：DE10234734A1

公开(公告)日：2004-02-12

申请号：DE10234734

申请日：2002-07-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKSCHIK STEFAN ,  HECHT THOMAS ,  SCHROEDER UWE ,  GOLDBACH MATTHIAS

IPC: H01L21/20 ,  H01L21/311 ,  H01L21/314 ,  H01L21/316 ,  H01L21/334 ,  H01L21/8242 ,  H01L21/22

Abstract: Method for processing a surface comprises (a) covering first sections of the surface with a metal oxide; (b) forming second sections in which the surface is exposed; and (c) modifying the surface exposed in the second sections.

公开(公告)号：DE10211932A1

公开(公告)日：2003-10-09

申请号：DE10211932

申请日：2002-03-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  GOLDBACH MATTHIAS

IPC: G11C7/06 ,  G11C11/4091 ,  G11C29/12 ,  G11C29/38 ,  G11C29/50

Abstract: A circuit arrangement includes a bit line ( 10 ), a reference bit line ( 12 ), a sense amplifier with two cross-coupled CMOS inverters, which in each case comprise an n-channel transistor ( 20, 22 ) and a p-channel field-effect transistor ( 30, 32 ), and also, at the respective source terminals, two voltage sources ( 40, 42 ), of which the voltage source ( 40 ) linked to the n-channel field-effect transistors can be driven from a lower through to an upper potential and the voltage source ( 42 ) linked to the p-channel field-effect transistors ( 30, 32 ) can be driven from the upper through to the lower potential. With this circuit arrangement, it is possible to store three different charge states in the memory cell ( 4 ) on the bit line ( 10 ) if the threshold voltages (U TH1 , U TH2 ) at the transistors are chosen to be greater than half the voltage difference between the lower and upper voltage potentials. This can be achieved by production engineering or, for example, by changing the substrate bias voltage. The third charge state can be utilized for binary logic or for detecting a defect in the memory cell ( 4 ).