-
公开(公告)号:DE502004003175D1
公开(公告)日:2007-04-19
申请号:DE502004003175
申请日:2004-09-03
Applicant: INFINEON TECHNOLOGIES AG
Inventor: HELNEDER JOHANN , SCHWERD MARKUS , GOEBEL THOMAS , MITCHELL ANDREA , KOERNER HEINRICH , HOMMEL MARTINA
IPC: H01L21/768 , H01L23/532
Abstract: A multifunctional dielectric layer can be formed on a substrate, especially on an exposed metallic strip conductor system on a substrate. An additional metal layer is formed across the surface of the exposed metal strip conductors. The metal layer is then at least partially converted to a nonconducting metal oxide, the dielectric layer.
-
公开(公告)号:DE102005045059A1
公开(公告)日:2007-03-29
申请号:DE102005045059
申请日:2005-09-21
Applicant: INFINEON TECHNOLOGIES AG
Inventor: SCHWERD MARKUS , KOERNER HEINRICH , HOMMEL MARTINA , SECK MARTIN
IPC: H01L23/522 , H01L27/08
-
公开(公告)号:DE102005045057A1
公开(公告)日:2007-03-22
申请号:DE102005045057
申请日:2005-09-21
Applicant: INFINEON TECHNOLOGIES AG
Inventor: SCHWERD MARKUS , KOERNER HEINRICH , HOMMEL MARTINA , SECK MARTIN
IPC: H01L23/522 , H01L23/64
Abstract: An integrated circuit (310) comprises an integrated element with conductive traces that are near the substrate (320), in the middle and far from the substrate respectively (324,328,334), spaced from the substrate in the same direction and having planar base and cover surfaces. The conductive traces are five or ten times longer than their width and the cover surface of the middle trace bounds the base of the upper trace and its base bounds the cover surface of the trace nearest the substrate. An independent claim is also included for an integrated circuit as above not having a middle trace.
-
公开(公告)号:DE10337569A1
公开(公告)日:2005-03-24
申请号:DE10337569
申请日:2003-08-14
Applicant: INFINEON TECHNOLOGIES AG
Inventor: HELNEDER JOHANN , GOEBEL THOMAS , SCHWERD MARKUS , MITCHELL ANDREA , KOERNER HEINRICH , SECK MARTIN , DREXL STEFAN , KLEIN WOLFGANG , HOMMEL MARTINA
IPC: H01L23/485 , H01L23/532 , H01L23/522 , H01L21/768
Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.
-
-
-