公开(公告)号：JP2002134708A

公开(公告)日：2002-05-10

申请号：JP2001211245

申请日：2001-07-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  ROEHR THOMAS ,  HOENIGSCHMID HEINZ

IPC: G11C11/14 ,  G11C7/18 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To reduce nonconforming action caused by overcoupling among the adjacent lines in a memory matrix, comprising a cell field composed of row lines and column lines in which the memory elements are situated at each point, where the row lines and column lines intersect one another, and the column line and/or row lines of the cell field are placed adjacent to each other. SOLUTION: This memory matrix is constituted, such that the order of row lines or column lines are equal in the edges of the memory matrix counterposed to each other regarding changes in the configurational constitution of the lines. As a result of this, additional circuit cost for executing address decoding, namely an additional circuit cost generated when an address line is not assigned correspondingly or it has a different order from the original order is avoided. For the case of MRAM, the connection constitution of the row lines and column lines in both edges of a cell field becomes advantageous. Furthermore, the cell field or its row lines and/or column line is made symmetrical by a mirror image, regarding changes in their arrangement constitution.

公开(公告)号：JP2001351376A

公开(公告)日：2001-12-21

申请号：JP2001106108

申请日：2001-04-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ESTERL ROBERT ,  HONIGSCHMID HEINZ ,  KANDOLF HELMUT ,  ROEHR THOMAS

IPC: G11C11/22

Abstract: PROBLEM TO BE SOLVED: To provide an operation method for integrated memory in which attenuation or damage of information stored in a memory cell is prevented. SOLUTION: Colum lines and substrate lines connected to a selected memory cell have an initial potential before being accessed, and activate row lines connected to the selected memory cell during one access, thereby, switch a selection transistor of the selected memory cell to be in a conduction state, apply a potential being different from a potential of a column line to the substrate line, evaluate and amplify potentials applied to the column lines at a first point of time, successively, apply the initial potential to the substrate line at a second point of time, successively, apply the initial potential to column lines at a third point of time. The first point of time, the second point of time, and the third point of time are selected so that a memory capacitor of the selected memory cell is charged and discharged by the same quantity every time.

公开(公告)号：JP2001283585A

公开(公告)日：2001-10-12

申请号：JP2001030127

申请日：2001-02-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ESTERL ROBERT ,  KANDOLF HELMUT ,  HONIGSCHMID HEINZ ,  ROEHR THOMAS

IPC: G11C11/22 ,  H01L21/8246 ,  H01L27/105

Abstract: PROBLEM TO BE SOLVED: To prevent change of memory contents caused by faulty voltage by connecting a column line and a charging line to a connection terminal 22 of a common power feeding potential GND in a non-active operation mode and in a common read-out amplifier or a driver circuit. SOLUTION: This integrated semiconductor memory is provided with a memory cell field having a ferroelectric memory effect memory cell MC, row lines WL1, and column lines BL1, the memory cell is inserted between one column line and a charging line PL1, the column line is connected to a read-out amplifier 2 from which an output signal S21 is taken, the charging line is connected to the driver circuit 3 connecting the amplifier 2 to a potential V1 and GND. and the column line and the charging line have an activation or a non-activation mode.

公开(公告)号：JP2000331474A

公开(公告)日：2000-11-30

申请号：JP2000130113

申请日：2000-04-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZORUTAN MANYOOKI ,  ROEHR THOMAS ,  BOEHM THOMAS

IPC: G11C14/00 ,  G11C7/06 ,  G11C7/10 ,  G11C11/22

Abstract: PROBLEM TO BE SOLVED: To reduce power consumption under an area required for column selection line path by connecting each bit line to a sense amplifier to which a bit line belongs through a first switching element, and connecting each bit line to a standby potential through a second switching element. SOLUTION: All column selection lines LCSLK takes a low potential so far as any column is not selected out of plural columns. Consequently, a first transistor A is made non-conduction state, and a second transistor B is conducted. Therefore, bit lines BL , bBL at the edge of cellfield AR are decoupled to a sense amplifier SA, and are in a standby potential VSTB. Consequently, a selection transistor T of a memory cell MC is made a non- conduction state. Thereby, contents of a memory of the memory cell MC is not affected at the time of access.

公开(公告)号：US6347059B2

公开(公告)日：2002-02-12

申请号：US81692501

申请日：2001-03-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  MANYOKI ZOLTAN ,  ESTERL ROBERT ,  ROEHR THOMAS

IPC: G11C11/22 ,  G11C7/02

CPC classification number: G11C11/22

Abstract: A semiconductor memory, in particular a ferroelectric semiconductor memory, has a differential write/read amplifier which is connected, via transfer transistors, to a bit line pair. The bit line pair includes a bit line and a corresponding reference bit line. The differential write/read amplifier is for reading data from and writing data to the memory capacitor (MC). In order to improve the accuracy of the bit line reference voltage, a main reference bit line is connected, via a charge switching element, to a reference voltage. At least one further reference bit line is connected to the main reference bit line via an equalization switching element for charge equalization between the reference bit lines.

Abstract translation: 半导体存储器，特别是铁电半导体存储器，具有通过传输晶体管连接到位线对的差分写/读放大器。 位线对包括位线和对应的参考位线。 差分写/读放大器用于从存储电容（MC）读取数据并将数据写入存储电容（MC）。 为了提高位线参考电压的精度，主参考位线经由充电开关元件连接到参考电压。 至少一个另外的参考位线通过用于参考位线之间的电荷均衡的均衡开关元件连接到主参考位线。

公开(公告)号：WO2004051666A3

公开(公告)日：2005-02-24

申请号：PCT/EP0312715

申请日：2003-11-13

Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KK ,  JACOB MICHAEL ,  REHM NORBERT ,  ROEHR THOMAS ,  TAKASHIMA DAISABURO

Inventor： JACOB MICHAEL ,  REHM NORBERT ,  ROEHR THOMAS ,  TAKASHIMA DAISABURO

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: A method for reducing noise coupling in a memory array is disclosed. The memory array includes a plurality memory cells interconnected by wordlines, bitlines, and platelines. The memory cells are arranged in columns having first and second bitlines coupled to a sense amplifier. During a memory access, at least adjacent bitlines pairs are not activated. The selected bitline pair or pairs are provided with a plateline pulse.

Abstract translation: 公开了一种减少存储器阵列中的噪声耦合的方法。 存储器阵列包括通过字线，位线和平行线互连的多个存储器单元。 存储器单元被布置成具有耦合到读出放大器的第一和第二位线的列。 在存储器访问期间，至少相邻的位线对不被激活。 选定的位线对或对配有一条平行线脉冲。

公开(公告)号：WO2004025664A3

公开(公告)日：2004-07-08

申请号：PCT/EP0309775

申请日：2003-09-03

Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KK

Inventor： TAKASHIMA DAISABURO ,  JACOB MICHAEL ,  JOACHIM HANS-OLIVER ,  ROEHR THOMAS ,  WOHLFAHRT JOERG

IPC: G11C29/50 ,  G11C29/00 ,  G11C11/22

CPC classification number: G11C29/50 ,  G11C11/22 ,  G11C2029/1204 ,  G11C2029/5004

Abstract: A test circuit for testing differential read signals during a memory access is disclosed. The test circuit is coupled to a pair of bitlines. During a read access, a selected memory cell produces a differential read signal on the bitlines. When the test circuit is activated, the magnitude of the differential read signal is varied. This enables easy testing of read signal margins in, for example, memory ICs.

Abstract translation: 公开了一种用于在存储器访问期间测试差分读取信号的测试电路。 测试电路耦合到一对位线。 在读取访问期间，所选择的存储器单元在位线上产生差分读取信号。 当测试电路被激活时，差分读取信号的幅度是变化的。 这使得能够容易地测试例如存储器IC中的读取信号余量。

公开(公告)号：WO2004029971A3

公开(公告)日：2004-06-03

申请号：PCT/EP0310468

申请日：2003-09-19

Applicant: INFINEON TECHNOLOGIES AG ,  TOSHIBA KK

Inventor： JOACHIM HANS-OLIVER ,  MIYAKAWA TADASHI ,  REHM NORBERT ,  ROEHR THOMAS

IPC: G11C29/00

CPC classification number: G11C29/785 ,  G11C17/14

Abstract: A redundancy unit (204) comprising first (260) and second (270) fuse blocks for programming the redundancy element (220) is disclosed. One fuse block has laser blowable fuses and the other electrical fuses. The redundancy unit can be programmed by either one of the fuse blocks, enabling the redundancy unit to able to be used for defects identified before and after packaging.

Abstract translation: 公开了一种包括用于对冗余元件（220）进行编程的第一（260）和第二（270））熔丝块的冗余单元（204）。 一个保险丝盒有激光熔断保险丝和其他电气保险丝。 冗余单元可以通过任一个保险丝块进行编程，使得冗余单元能够用于包装之前和之后识别的缺陷。

公开(公告)号：WO0239455A8

公开(公告)日：2002-10-17

申请号：PCT/DE0104232

申请日：2001-11-12

Applicant: INFINEON TECHNOLOGIES AG ,  BOEHM THOMAS ,  HOENIGSCHMID HEINZ ,  ROEHR THOMAS

Inventor： BOEHM THOMAS ,  HOENIGSCHMID HEINZ ,  ROEHR THOMAS

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

CPC classification number: G11C11/16

Abstract: The invention relates to an MRAM arrangement, comprising a selection transistor (T), connected to several MTJ memory cells (1) and with an increased channel width.

公开(公告)号：WO2004047116A8

公开(公告)日：2004-08-26

申请号：PCT/SG0300263

申请日：2003-11-11

Applicant: INFINEON TECHNOLOGIES AG ,  JACOB MICHAEL ,  ROEHR THOMAS ,  WOHLFAHRT JOERG ,  JOACHIM HANS-OLIVER

Inventor： JACOB MICHAEL ,  ROEHR THOMAS ,  WOHLFAHRT JOERG ,  JOACHIM HANS-OLIVER

IPC: G11C29/50 ,  G11C29/00

CPC classification number: G11C29/50 ,  G11C11/22

Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effect into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data. The capacitor connects a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines. A potential is connected to the first bit line through a third transistor and changes a pre-charge signal level on the first bit line when the third transistor is turned on to reduce the differential read signal.

Abstract translation: 本发明提供了一种测试模式部分，用于促进信号余量的最坏情况产品测试序列，以确保在整个组件使用寿命期内产生全部产品功能，从而考虑到所有的老化效应。 半导体存储器测试模式配置包括用于存储数字数据的第一电容器。 电容器通过第一选择晶体管将单元板线连接到第一位线。 第一个选择晶体管通过与字线的连接来激活。 第二电容器存储数字数据，并通过第二选择晶体管将单元板线连接到第二位线。 第二选择晶体管也通过与字线的连接来激活。 读出放大器连接到第一和第二位线，并测量第一和第二位线上的差分读取信号。 电位通过第三晶体管连接到第一位线，并且当第三晶体管导通时改变第一位线上的预充电信号电平以减小差分读取信号。