公开(公告)号：DE102004014925A1

公开(公告)日：2005-10-13

申请号：DE102004014925

申请日：2004-03-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTH HANS-JOACHIM ,  SCHRUEFER KLAUS ,  RUSCH ANDREAS

IPC: H01L23/525

Abstract: An electronic circuit arrangement in accordance with some embodiments has a substrate, the substrate including: a plurality of metallization layers located one above the other; a single fuse-link via coupled between a first metallization layer and a second metallization layer of the plurality of metallization layers, wherein the single fuse-link via is in the form of an electrical fuse link preferentially programmable by applying a sufficiently large current to melt or degenerate the fuse link; a plurality of through-contact vias coupled in parallel between a third metallization layer and a fourth metallization layer of the plurality of metallization layers, wherein the through-contact vias form a through-contact between the third and fourth metallization layers; and electrical circuit components, arranged in a circuit layer, which are electrically coupled to one another by means of the single fuse-link via and by means of the plurality of through-contact vias.

公开(公告)号：DE10344604A1

公开(公告)日：2005-05-04

申请号：DE10344604

申请日：2003-09-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTH HANS-JOACHIM ,  SCHRUEFER KLAUS ,  OSTERMAYR MARTIN ,  OLBRICH ALEXANDER

IPC: G11C11/405 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/108 ,  H01L27/11

Abstract: A memory cell having three transistors and a capacitor having metallic electrodes is described. Multiple memory cells may be arranged in a memory unit or array. Collective electrodes may be used in a space-saving embodiment of the capacitor.

公开(公告)号：DE102009049775A1

公开(公告)日：2011-04-07

申请号：DE102009049775

申请日：2009-06-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUSS CHRISTIAN ,  PACHA CHRISTIAN ,  JENEI SNEZANA ,  SCHRUEFER KLAUS

IPC: H01L21/8249 ,  H01L21/84 ,  H01L23/60 ,  H01L27/06 ,  H01L27/082 ,  H01L27/085 ,  H01L27/12

公开(公告)号：DE502004011345D1

公开(公告)日：2010-08-12

申请号：DE502004011345

申请日：2004-11-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHRUEFER KLAUS

IPC: H01L29/786 ,  H01L29/80

公开(公告)号：DE10360874B4

公开(公告)日：2009-06-04

申请号：DE10360874

申请日：2003-12-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHRUEFER KLAUS

IPC: H01L29/78 ,  H01L21/336 ,  H01L27/092 ,  H01L29/786 ,  H01L29/80

Abstract: A field effect transistor with a heterostructure includes a strained monocrystalline semiconductor layer formed on a carrier material, which has a relaxed monocrystalline semiconductor layer made of a first semiconductor material (Si) as the topmost layer. The strained monocrystalline semiconductor layer has a semiconductor alloy (GexSi1-x), where the proportion x of a second semiconductor material can be set freely. Furthermore, a gate insulation layer and a gate layer are formed on the strained semiconductor layer. To define an undoped channel region, drain/source regions are formed laterally with respect to the gate layer at least in the strained semiconductor layer. The possibility of freely setting the Ge proportion x enables a threshold voltage to be set as desired, whereby modern logic semiconductor components can be realized.

公开(公告)号：DE102008000319A1

公开(公告)日：2008-10-16

申请号：DE102008000319

申请日：2008-02-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAKOSCHKE RONALD ,  SCHRUEFER KLAUS

IPC: H01L27/105 ,  H01L27/115 ,  H01L27/24

Abstract: A memory element includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element.

公开(公告)号：DE102004052388A1

公开(公告)日：2006-05-04

申请号：DE102004052388

申请日：2004-10-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTH HANS-JOACHIM ,  SCHRUEFER KLAUS

IPC: H01L29/78 ,  H01L21/336

公开(公告)号：DE102004044667A1

公开(公告)日：2006-03-16

申请号：DE102004044667

申请日：2004-09-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEWS HELMUT ,  HOLZ JUERGEN ,  SCHRUEFER KLAUS

IPC: H01L29/78 ,  H01L21/336

公开(公告)号：DE10246718A1

公开(公告)日：2004-04-22

申请号：DE10246718

申请日：2002-10-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEWS HELMUT ,  SCHRUEFER KLAUS ,  HOLZ JUERGEN

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/78

Abstract: Field effect transistor comprises a semiconductor substrate (1), a source recess (SV) and a drain recess (DV) formed in the substrate, a recessed insulating layer (VI) formed in the base region of the source and drain recess, an electrically conducting filler layer (F) formed on the surface of the insulating layer, a gate dielectric (3) formed on the substrate surface between the source and drain recesses, and a gate layer (4) formed on the surface of the gate dielectric. An Independent claim is also included for a process for the production of a field effect transistor.