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公开(公告)号：JP2006024330A
公开(公告)日：2006-01-26
申请号：JP2004203670
申请日：2004-07-09
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： FIFIELD JOHN A , KARTSCHOKE PAUL D , KLAASEN WILLIAM A , KOSONOCKY STEPHEN V , RANDY W MANN , OPPOLD JEFFERY H , ROHRER NORMAN J
IPC: G11C11/41 , G01T1/17 , G11C29/04 , H01L21/8238 , H01L27/092
Abstract: PROBLEM TO BE SOLVED: To provide a detection circuit and a method for detecting silicon well voltage or current indicating collision of an alpha particle or a cosmic ray to the silicon well in silicon substrate.
SOLUTION: An effective application of the detection circuit is use in redundancy repair latches used for an SRAM. In the redundancy repair latches, normally writing is once performed when power is on in order to register wrong latch data, though writing is not performed again usually. When either state of these latches is altered by SER phenomena (soft error rate: collision of the alpha particle or the cosmic ray, and the like), the recovery data for the redundant latch of the SRAM is mapped incorrectly. In this detection circuit and the method, whether the SER phenomenon occurs in these latches is monitored, when occurring, reloading the recovery data is performed to the redundancy repair latches.
COPYRIGHT: (C)2006,JPO&NCIPIAbstract translation: 要解决的问题：提供检测电路和检测硅阱电压或电流的方法，所述硅阱电压或电流指示α粒子或宇宙射线与硅衬底中的硅阱的碰撞。
解决方案：检测电路的有效应用是用于SRAM的冗余修复锁存器中。 在冗余修复锁存器中，通常只有在通电时才进行写入操作，才能注册错误的锁存器数据，但通常不会再写入。 当这些锁存器的任一状态被SER现象（软错误率：α粒子或宇宙射线的碰撞等）改变时，SRAM的冗余锁存器的恢复数据被映射不正确。 在该检测电路和方法中，监视这些锁存器中是否发生SER现象，发生时，对冗余修复锁存器进行恢复数据的重新加载。 版权所有（C）2006，JPO＆NCIPI
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12.发明专利
公开(公告)号：JP2003030987A
公开(公告)日：2003-01-31
申请号：JP2002142731
申请日：2002-05-17
Inventor： FIFIELD JOHN A , STORASKA DANIEL W , WIN K RUK , STEPHENS JEREMY K , KIRIHATA TOSHIAKI
IPC: G11C11/409 , G11C7/06 , G11C11/4091
CPC classification number: G11C7/067 , G11C7/062 , G11C11/4091
Abstract: PROBLEM TO BE SOLVED: To provide a memory architecture, in which coupling noise between bit lines is small at CMOS intersection coupling sensing operation, and which operates at a high speed.
SOLUTION: In a single bit-line direct sensing architecture, a sense amplifier circuit, having four transistors arranged for each memory array, is used. In this circuit, the transistor functions so that a data bit from a true bit-line of a pair of bit line or an auxiliary bit line is transferred selective to a data line. The data line is preferably arranged on a plurality of memory arrays, and the data line may not be required, to share in read operation and write operation. Furthermore, digital sensing scheme function is performed, by charging a data line during read-out operation using one more current source detecting the ratio of a current source, driving by a bit line of a corresponding array and resistance of a transistor.
COPYRIGHT: (C)2003,JPOAbstract translation: 要解决的问题：提供一种存储架构，其中位线之间的耦合噪声在CMOS交叉耦合感测操作处较小，并且以高速运行。 解决方案：在单个位线直接感测架构中，使用具有为每个存储器阵列布置的四个晶体管的读出放大器电路。 在该电路中，晶体管起作用，使得来自一对位线或辅助位线的真位置的数据位被选择性地传送到数据线。 数据线优选地布置在多个存储器阵列上，并且可能不需要数据线，以共享读操作和写操作。 此外，通过使用检测电流源的比例的一个电流源，通过相应阵列的位线驱动和晶体管的电阻来驱动读出操作期间的数据线，执行数字感测方案功能。
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公开(公告)号：JP2000236242A
公开(公告)日：2000-08-29
申请号：JP2000017125
申请日：2000-01-26
Applicant: INFINEON TECHNOLOGIES CORP , IBM
Inventor： CHU ALBERT M , FIFIELD JOHN A , ROTELLA JASON E , DORTU JEAN-MARC
Abstract: PROBLEM TO BE SOLVED: To obtain a circuit which is improved in the timing between input and output pulse trains. SOLUTION: This circuit is equipped with a delay lock loop 32 which has a receiver 33, a pulse generator 36, a logic network 50, and a variable delay line 34, and extract two pulse trains having side edges of the same type from the leading and trailing edges of the input pulse train, selects the time delay degree of the variable delay line, and generates a combined output pulse train which has a predetermined phase relation with the input pulse train.
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公开(公告)号：CA2002362A1
公开(公告)日：1990-09-10
申请号：CA2002362
申请日：1989-11-07
Applicant: IBM
Inventor： BLAKE ROBERT M , BOSSEN DOUGLAS C , CHEN CHIN L , FIFIELD JOHN A , KALTER HOWARD L , LO TIN C
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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Patent Agency Ranking
公开(公告)号：AU2003304110A1
公开(公告)日：2004-11-26
申请号：AU2003304110
申请日：2003-04-30
Applicant: IBM
Inventor： TONTI WILLIAM R , BERRY WAYNE S , FIFIELD JOHN A , GUTHRIE WILLIAM H , KONTRA RICHARD S
IPC: H01L23/525 , H01L29/00 , H01L21/44
Abstract: A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.
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公开(公告)号：CA2034027C
公开(公告)日：1995-12-19
申请号：CA2034027
申请日：1991-01-11
Applicant: IBM
Inventor： BARTH JOHN E JR , DRAKE CHARLES E , FIFIELD JOHN A , HOVIS WILLIAM P , KALTER HOWARD L , LEWIS SCOTT C , NICKEL DANIEL J , STAPPER CHARLES H , YANKOSKY JAMES A
IPC: G11C11/401 , G06F11/10 , G11C29/00 , G11C29/42 , G11C7/00
Abstract: A DRAM having on-chip ECC and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section, and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry is optimized to reduce the access delays introduced by-carrying out on-chip error correction. The ECC block provides both the corrected data bits and the check bits to an SRAM. Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.
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公开(公告)号：CA2034027A1
公开(公告)日：1991-08-14
申请号：CA2034027
申请日：1991-01-11
Applicant: IBM
Inventor： BARTH JOHN E JR , DRAKE CHARLES E , FIFIELD JOHN A , HOVIS WILLIAM P , KALTER HOWARD L , LEWIS SCOTT C , NICKEL DANIEL J , STAPPER CHARLES H , YANKOSKY JAMES A
IPC: G11C11/401 , G06F11/10 , G11C29/00 , G11C29/42 , G11C7/00
Abstract: A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.
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公开(公告)号：CA2002362C
公开(公告)日：1994-02-01
申请号：CA2002362
申请日：1989-11-07
Applicant: IBM
Inventor： BLAKE ROBERT M , BOSSEN DOUGLAS C , CHEN CHIN L , FIFIELD JOHN A , KALTER HOWARD L , LO TIN C
Abstract: FAULT TOLERANT COMPUTER MEMORY SYSTEMS AND COMPONENTS EMPLOYING DUAL LEVEL ERROR CORRECTION AND DETECTION WITH LOCK-UP FEATURE In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：CA2002361C
公开(公告)日：1993-12-21
申请号：CA2002361
申请日：1989-11-07
Applicant: IBM
Inventor： BLAKE ROBERT M , BOSSEN DOUGLAS C , CHEN CHIN L , FIFIELD JOHN A , KALTER HOWARD L
Abstract: FAULT TOLERANT COMPUTER MEMORY SYSTEMS AND COMPONENTS EMPLOYING DUAL LEVEL ERROR CORRECTION AND DETECTION WITH DISABLEMENT FEATURE In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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