公开(公告)号：EP1872409A4

公开(公告)日：2009-12-30

申请号：EP06750619

申请日：2006-04-19

Applicant: IBM

Inventor： ZHU WENJUAN ,  CHUDZIK MICHAEL P ,  GLUSCHENKOV OLEG ,  PARK DAE-GYU ,  SEKIGUCHI AKIHISA

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/28097 ,  H01L21/28229 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517

公开(公告)号：JP2004153256A

公开(公告)日：2004-05-27

申请号：JP2003347641

申请日：2003-10-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GLUSCHENKOV OLEG ,  HEGDE SURYANARAYAN G ,  TEWS HELMUT H

IPC: H01L21/316 ,  H01L21/314 ,  H01L21/321 ,  H01L29/78

CPC classification number: H01L21/3144 ,  H01L21/3141 ,  H01L21/32105

Abstract: PROBLEM TO BE SOLVED: To provide an improved method for growing high quality oxide on a composite face of a silicon substrate having at least two crystal orientations.
SOLUTION: Formation of a vertical MOS transistor on a silicon wafer or formation of another 3 dimensional integrated circuit structure expose two faces having at least two different crystal orientations. Since interatomic spaces are different for the different faces, the oxides on the different crystal faces grow at essentially different speeds. When the silicon is heated in a nitrogen-containing atmosphere to form a thin layer of nitrogen, and then the oxide is grown via a thin nitrided layer, variations of the thickness of the oxide are reduced to less than 1 %.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004214631A

公开(公告)日：2004-07-29

申请号：JP2003400729

申请日：2003-11-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOKUMACI OMER H ,  GLUSCHENKOV OLEG ,  BELYANKSY MICHAEL ,  DORIS BRUCE B

IPC: H01J1/312 ,  H01L21/00 ,  H01L21/033 ,  H01L21/205 ,  H01L21/425 ,  H01L29/06 ,  H01L29/76 ,  H01L31/0336 ,  H01L31/0352

CPC classification number: B82Y30/00 ,  B82Y10/00 ,  B82Y20/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/0332 ,  H01L21/0337 ,  H01L31/0352

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a uniform layer structure, including an ultra-thin layer of amorphous silicon and a thermal oxide thereof. SOLUTION: In one side surface, the present invention is a method for forming the nano-laminate of an oxidized silicon on a substrate. In the other side surface, the invention is a method for forming a patterned hard mask on the substrate. The patterned hard mask includes the nano-laminate of a silicon and the oxidized silicon. The methods are characterized by the oxidization of an amorphous silicon layer using atomic oxygen. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004193588A

公开(公告)日：2004-07-08

申请号：JP2003389984

申请日：2003-11-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LEWIS L SUU ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: G11C11/412 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12

CPC classification number: H01L27/11 ,  G11C11/412 ,  H01L21/84 ,  H01L27/1104 ,  H01L27/1203

Abstract: PROBLEM TO BE SOLVED: To provide an SRAM cell design capable of simultaneously attaining high performance, low power, and small chip size by using only vertical MOSFET device including a peripheral (transmission) gate. SOLUTION: A method for forming a SRAM cell device comprises the steps of forming a pass gate FET transistor in a silicon layer formed on a flat insulating material and a parallel island, and further forming a pair of vertical pulldown FET transistors having a first common body and a first common source region. The method further forms a pulldown separation space for dividing an upper layer of a pullup and pulldown drain region of a pair of vertical pulldown FET transistor in two by etching through the upper diffusion between cross-linked inverter FET transistors, and the separation space reaches the common boby layer. The method further comprises the steps of forming a pair of vertical pullup FET transistor having a second common body and a second common drain, and connecting the FET transistor so as to form a SRAM cell. COPYRIGHT: (C)2004,JPO&NCIPI

Abstract translation: 要解决的问题：通过仅使用包括外围（传输）门的垂直MOSFET器件，提供能够同时获得高性能，低功率和小芯片尺寸的SRAM单元设计。 解决方案：一种用于形成SRAM单元器件的方法包括以下步骤：在形成于平坦绝缘材料和平行岛上的硅层中形成栅极FET晶体管，并进一步形成一对垂直下拉FET晶体管，其具有 第一共同体和第一共同源区。 该方法进一步形成一个下拉分离空间，用于通过在交联的反相FET晶体管之间的上部扩散进行蚀刻，将一对垂直下拉式FET晶体管的上拉和下拉漏极区的上层分成两层，分离空间达到 普通boby层。 该方法还包括以下步骤：形成具有第二公共体和第二公共漏极的一对垂直上拉FET晶体管，并连接FET晶体管以形成SRAM单元。 版权所有（C）2004，JPO＆NCIPI

公开(公告)号：WO02099866A3

公开(公告)日：2003-08-28

申请号：PCT/EP0206916

申请日：2002-06-04

Applicant: IBM ,  COMPANIE IBM FRANCE

Inventor： BALLANTINE ARNE W ,  FALTERMEIER JONATHAN E ,  FLAITZ PHILIP L ,  GILBERT JEFFREY D ,  GLUSCHENKOV OLEG ,  HEENAN CAROL J ,  JAMMY RAJARAO

IPC: H01L21/28 ,  H01L21/3105 ,  H01L21/314 ,  H01L21/316 ,  H01L21/321 ,  H01L21/334 ,  H01L21/8234 ,  H01L29/51

CPC classification number: H01L21/28202 ,  H01L21/3105 ,  H01L21/3144 ,  H01L21/31662 ,  H01L21/32105 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66181

Abstract: Disclosed is a method to convert a stable silicon nitride film (101)covering a silicon substrate (100) into a stable silicon oxide film (102) with a low content of residual nitrogen in the resulting silicon oxide film. This is achieved by performing the steps of (i)providing a low pressure environment for the silicon nitride fim of between about l.33 X10 Pa(100 Torr) to about 13.3 Pa (0.1 Torr);(ii)introducing hydrogen and oxygen into said low pressure environment; and iii maintaining said low pressure environment at a temperature of about 600°C to about 1200 C° for a predetermined amount of time. This is an unexpectedand unique property of the in situ steam generation process since both silicon nitride and silicon oxide materials are chemically very stable compounds. Application of the claimed method to the art of microelectronic device fabrication, such as fabrication of on-chip dielectric capacitors and metal insulator semiconductor field effect transistors, is also disclosed.

Abstract translation: 公开了一种将覆盖硅衬底（100）的稳定氮化硅膜（101）转换成所得氧化硅膜中残留氮含量低的稳定氧化硅膜（102）的方法。 这通过以下步骤来实现：（i）为约13.3×10 4 Pa（100托）至约13.3Pa（0.1托）的氮化硅膜提供低压环境;（ii）引入氢 和氧气进入所述低压环境; 以及iii将所述低压环境保持在约600℃至约1200℃的温度下一段预定的时间。 这是原位蒸汽产生过程的意想不到的独特性质，因为氮化硅和氧化硅材料都是化学上非常稳定的化合物。 还公开了所要求保护的方法应用于微电子器件制造领域，例如制造片上电介质电容器和金属绝缘体半导体场效应晶体管。

公开(公告)号：WO2006107669A3

公开(公告)日：2009-04-09

申请号：PCT/US2006011391

申请日：2006-03-29

Applicant: IBM ,  BELYANSKY MICHAEL P ,  GLUSCHENKOV OLEG ,  LI YING ,  MALLIKARJUNAN ANUPAMA

Inventor： BELYANSKY MICHAEL P ,  GLUSCHENKOV OLEG ,  LI YING ,  MALLIKARJUNAN ANUPAMA

IPC: H01L21/26

CPC classification number: H01L21/3185 ,  C23C16/345 ,  C23C16/45523 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7833 ,  H01L29/7843

Abstract: A method for increasing the level of stress for amorphous thin film stressors by means of modifying the internal structure of such stressors is provided. The method includes first forming a first portion of an amorphous film stressor material (14) on at least a surface of a substrate (12), said first portion (18) having a first state of mechanical strain defining a first stress value. After the forming step, the first portion of the amorphous film stressor material is densified (20) such that the first state of mechanical strain is not substantiaUydtered,\vhile increasing the first stress value. In some embodiments, the steps of forming and densifying are repeated any number of times (20, 2OA, 20B) to obtain a preselected and desired thickness for the stressor.

Abstract translation: 提供了一种通过改变这种压力源的内部结构来提高非晶薄膜应力的应力水平的方法。 该方法包括首先在衬底（12）的至少一个表面上形成非晶膜应力材料（14）的第一部分，所述第一部分（18）具有限定第一应力值的第一机械应变状态。 在成形步骤之后，无定形薄膜应力材料的第一部分被致密化（20），使得机械应变的第一状态没有被证实，即增加第一应力值。 在一些实施例中，形成和致密化的步骤重复任意次数（20,20A，20B），以获得应力源的预选和期望的厚度。

公开(公告)号：JP2005260228A

公开(公告)日：2005-09-22

申请号：JP2005059899

申请日：2005-03-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： RAMACHANDORA DEIVAKARUNI ,  GLUSCHENKOV OLEG ,  KWON OH-JUNG ,  RAJEEV MALIK

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/8234 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/088 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/10894 ,  H01L27/10861 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure to resolve problems in word line continuity and support region punch-through, and to provide a manufacturing method therefor. SOLUTION: An integrated circuit comprises at least one semiconductor memory array and a logic circuit. The memory array includes conductive word lines. The logic circuit includes a logic transistor having a conductive gate. The gate of the logic transistor and the word lines are composed of polysilicon and metal layers. In the word lines, the metal layer is thicker than the polysilicon layer. In the gate of the logic transistor, the metal layer is thinner than the polysilicon layer. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供解决字线连续性和支撑区域穿透中的问题的结构，并提供其制造方法。 解决方案：集成电路包括至少一个半导体存储器阵列和逻辑电路。 存储器阵列包括导电字线。 逻辑电路包括具有导电栅极的逻辑晶体管。 逻辑晶体管的栅极和字线由多晶硅和金属层组成。 在字线中，金属层比多晶硅层厚。 在逻辑晶体管的栅极中，金属层比多晶硅层薄。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2002124672A

公开(公告)日：2002-04-26

申请号：JP2001193470

申请日：2001-06-26

Applicant: IBM

Inventor： CLEVENGER LAWRENCE ALFRED ,  MANDELMAN JACK A ,  JAMMY RAJARO ,  GLUSCHENKOV OLEG ,  MCSTAY IRENE LENNOX ,  WONG KWONG HON ,  FALTERMEIER JONATHAN

IPC: H01L29/43 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a gate structure for MOSFETs for application of the CMOS technology, etc., which is durable against high temperature processes such as junction activation, etc., and reduces the gate propagation delay. SOLUTION: The gate structure 10 has an insulation layer 14 on a semiconductor substrate 12, and a polysilicon gate electrode 16 on the insulation layer 14. The gate structure 10 comprises a diffused barrier layer 20 having semi- insulative characteristics on the gate electrode 16, and a gate conductor 18 on the barrier layer 20. The conductor 18 is electrically contacted to the gate electrode 16. The constitution and the thickness of the barrier layer 20 are adjusted so as to effectively block the diffusion and the mixing between the gate conductor 18 and the gate electrode 16, but realize a capacitive coupling and/or a leak current not so increasing the gate propagation delayer of the gate surface 10.

公开(公告)号：WO2007038237A3

公开(公告)日：2007-07-26

申请号：PCT/US2006036916

申请日：2006-09-22

Applicant: IBM ,  CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  BELYANSKY MICHAEL

Inventor： CHIDAMBARRAO DURESETI ,  DOKUMACI OMER ,  GLUSCHENKOV OLEG ,  BELYANSKY MICHAEL

IPC: H01L21/28 ,  H01L29/40

CPC classification number: H01L29/512 ,  H01L21/26586 ,  H01L21/31155 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

Abstract: The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i-e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying gate conductors has vertical edges; a first gate oxide located beneath the at least one overlaying gate conductor, the first gate oxide not extending beyond the vertical edges of the at least overlaying gate conductor; and a second gate oxide located beneath at least a portion of the at one overlaying gate conductor. In accordance with the present invention, the first gate oxide and the second gate oxide are selected from high k oxide-containing materials and low k oxide-containing materials, and the first gate oxide is higher k than the second gate oxide or vice-versa.

Abstract translation: 本发明提供一种半导体结构，其具有至少一个CMOS器件，其中米勒电容，即重叠电容，并且驱动电流得到改善。 本发明的结构包括具有至少一个覆盖栅极导体的半导体衬底，所述至少一个覆盖栅极导体中的每一个具有垂直边缘; 位于所述至少一个覆盖栅极导体下方的第一栅极氧化物，所述第一栅极氧化物不延伸超过所述至少覆盖栅极导体的垂直边缘; 以及位于一个重叠栅极导体的至少一部分下方的第二栅极氧化物。 根据本发明，第一栅极氧化物和第二栅极氧化物选自含高K氧化物的材料和低K氧化物的材料，并且第一栅极氧化物比第二栅极氧化物高k，反之亦然 。

公开(公告)号：WO2005050701A8

公开(公告)日：2005-11-03

申请号：PCT/US2004037434

申请日：2004-11-09

Applicant: IBM ,  DORIS BRUCE B ,  BELYANSKY MICHAEL P ,  BOYD DIANE C ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG

Inventor： DORIS BRUCE B ,  BELYANSKY MICHAEL P ,  BOYD DIANE C ,  CHIDAMBARRAO DURESETI ,  GLUSCHENKOV OLEG

IPC: H01L21/8238 ,  H01L31/119 ,  H01L21/302 ,  H01L21/336 ,  H01L21/461 ,  H01L31/113

CPC classification number: H01L29/7845 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28247 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1083 ,  H01L29/4925 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of fabricating a semiconductor device structure, includes: providing a substrate (1), providing an electrode (6) on the substrate (1), forming a recess (12) in the electrode (6), the recess having an opening, disposing a small grain semiconductor material (17) within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

Abstract translation: 一种制造半导体器件结构的方法，包括：提供衬底（1），在所述衬底（1）上提供电极（6），在所述电极（6）中形成凹部（12），所述凹部具有开口， 在凹部内设置小晶粒半导体材料（17），在凹部内覆盖开口以容纳小晶粒半导体材料，然后对所得结构进行退火。