公开(公告)号：EP1470583A4

公开(公告)日：2005-08-03

申请号：EP02789958

申请日：2002-11-26

Applicant: IBM

Inventor： POGGE BERNHARD H ,  YU ROY ,  PRASAD CHANDRIKA ,  NARAYAN CHANDRASEKHAR

IPC: H01L23/12 ,  H01L21/68 ,  H01L21/768 ,  H01L23/48 ,  H01L23/485 ,  H01L23/525 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L24/10 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0652 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate (1). A metallized feature (2) is formed in the top surface of a substrate, and a handling plate (35) is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via (20). The substrate may comprise a chip (44) having a device (30), e.g. a PE chip. The plate may be a wafer (65) attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices (30,60) fabricated therein, so that the process provides vertical wafer-level integration of the devices.

公开(公告)号：EP0806727A3

公开(公告)日：1998-05-20

申请号：EP97302760

申请日：1997-04-22

Applicant: IBM

Inventor： ALT PAUL MATTHEW ,  CHALCO PEDRO A ,  FURMAN BRUCE KENNETH ,  HORTON RAYMOND ROBERT ,  NARAYAN CHANDRASEKHAR ,  OWENS BENAL LEE JR ,  WARREN KEVIN WILSON ,  WRIGHT STEVEN LORENZ

IPC: G02F1/1343 ,  G02F1/13 ,  G02F1/1362 ,  G06F11/20 ,  G09F9/30 ,  G09G3/20 ,  G09G3/36 ,  G11C29/00

CPC classification number: G02F1/1309 ,  G02F2001/136272 ,  G09G3/3611 ,  G09G3/3685 ,  G09G2300/0426 ,  G09G2310/0297 ,  G09G2330/08 ,  G11C29/76 ,  Y10S345/904

Abstract: A matrix addressed display system designed so as to enable data line (22) repair by electronic mechanisms which is efficient and low in cost and thus increases yield. Such active data line (22) repair utilizes additional data driver (36) outputs, a defect map memory (48) in the TFT/LCD module and modification of the data stream to the data drivers (36) by additional circuits (42) between the display and the display adapter. A bus configuration on the display substrate is utilized which combines repair flexibility, low parasitic capacitance, and the ability to easily make the necessary interconnections. The number of interconnections is kept to a minimum, the connections are reliable, and the connections may be made with conventional wire bond or laser bond technology, or disk bond technology.

公开(公告)号：JP2004193605A

公开(公告)日：2004-07-08

申请号：JP2003405153

申请日：2003-12-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DALTON TIMOTHY J ,  DAS SANJIT K ,  ENGEL BRETT H ,  HERBST BRIAN W ,  HICHRI HABIB ,  KASTENMEIER BERND E ,  MALONE KELLY ,  MARINO JEFFREY R ,  MARTIN ARTHUR ,  MCGAHAY VINCENT J ,  MELVILLE IAN D ,  NARAYAN CHANDRASEKHAR ,  PETRARCA KEVIN S ,  VOLANT RICHARD P

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76808 ,  H01L21/76801 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for reducing thermal mechanical stress in stack and via. SOLUTION: An interconnection structure for a semiconductor device comprises an organic low-k (low specific dielectric constant) dielectric layer formed on a lower metallization. The via to be formed here is in this low-k dielectric layer, and combines a lower metallization line formed on the lower metallization level and an upper metallization line formed on an upper metallization level. This via is surrounded by structure collar selected from material with CTE that can protect the via from shearing force generated after the thermal expansion of the low-k dielectric layer. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004006772A

公开(公告)日：2004-01-08

申请号：JP2003093635

申请日：2003-03-31

Applicant: IBM ,  SIEMENS AG

Inventor： NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL ,  KIEWRA EDWARD ,  RADENS CARL

IPC: B23K26/00 ,  B23K26/38 ,  B23K101/38 ,  H01H69/02 ,  H01H85/00 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/525 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit having an improved fuse structure part and laser fuse links. SOLUTION: The fuse structure part in an integrated circuit chip comprises an insulated semiconductor substrate, a fuse bank 410 which is constituted of a plurality of the parallel fuse links 402, 404 and 404 on the same plane and which are integrated with the insulated semiconductor substrate and voids 410 and 412 which scatter between pairs of fuse links and which extend across the plane delimited by the fuse links on the same plane. The voids 410 and 412 surrounding a spot 420 to be hit by a laser beam during a fusing operation function as crack stops for preventing damage against an adjacent circuit element or the other existing fuse link. Thus, a denser pitch between fuses can be obtained by suitably forming and positioning the voids. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2000058655A

公开(公告)日：2000-02-25

申请号：JP17440199

申请日：1999-06-21

Applicant: IBM

Inventor： ARNDT KENNETH C ,  GAMBINO JEFFREY P ,  MANDELMAN JACK A ,  NARAYAN CHANDRASEKHAR ,  SCHNABEL RAINER F ,  SCHUTZ RONALD J ,  TOEBBEN DIRK

IPC: H01L21/82 ,  H01L21/768 ,  H01L23/525

Abstract: PROBLEM TO BE SOLVED: To improve the control of thickness of an insulator layer on a fuse structure, by a method wherein a dielectric structure is positioned on a conduction level, and electric connection is performed at a selected position of the conduction level through the dielectric structure. SOLUTION: On a semiconductor substrate 10 an electric conduction level 1 is formed by using conductive material selected out of aluminum, copper, aluminum copper alloy, and doped polysilicon having metal type conductivity. A dielectric etching stop material layer 2 is stuck on the upper surface of the electric conduction level 1. Electric connection is performed to a selected position of the electric conduction level 1 through the dielectric etching stop material layer 2, and a conductive fuse 21 is constituted. As a result control of the thickness of an insulator layer on the fuse structure containing a self-aligned isolation cap can be improved.

公开(公告)号：JP2000323578A

公开(公告)日：2000-11-24

申请号：JP37247499

申请日：1999-12-28

Applicant: IBM ,  SIEMENS AG

Inventor： NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL ,  KIEWRA EDWARD ,  RADENS CARL

IPC: B23K26/00 ,  B23K26/38 ,  B23K101/38 ,  H01H69/02 ,  H01H85/00 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/525 ,  H01L27/04 ,  H01L27/108 ,  H01H85/046

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit which has a improved fuse structure and a laser fuse link. SOLUTION: A fuse structure within an integrated circuit chi is described which includes an insulated semiconductor substrate, a fuse band 4 consisting of a plurality of parallel fuse links 402, 404, and 406 on the same plane and united with the insulated semiconductor substrate, and voids 410 and 412 scattered among fuse links each in a pair and extending beyond the plane demarcated by the fuse links on the same plane. The voids 410 and 412, surrounding the spot 420 which should be hit with a laser beam during the operation of fuse fusion function as crack stopper for preventing damages to the adjacent circuit element or other existing fuse link. Closer pitch between fuses can be obtained by forming and positioning the voids properly.

公开(公告)号：JPH1039790A

公开(公告)日：1998-02-13

申请号：JP9898197

申请日：1997-04-16

Applicant: IBM

Inventor： ALT PAUL MATTHEW ,  CHALCO PEDRO A ,  FURMAN BRUCE KENNETH ,  HORTON RAYMOND ROBERT ,  NARAYAN CHANDRASEKHAR ,  OWENS BENAL LEE JR ,  WARREN KEVIN WILSON ,  WRIGHT STEVEN LORENZ

IPC: G02F1/1343 ,  G02F1/13 ,  G02F1/1362 ,  G06F11/20 ,  G09F9/30 ,  G09G3/20 ,  G09G3/36 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To make possible easily and inexpensively repairing an omission in a data line by selectively activating a selected non-committed data driver and providing a data signal on a conductive line. SOLUTION: In an array 32, the number of output lines of respective data drivers 36 are increased for adding an auxiliary driver to a glass panel 34. An electric connector used for connecting an LCD panel to a data source of a host computer, etc., requires a PROM chip selecting excess line only by a piece, and other PROM signals are multiplexed by existing lines. After reset, a controller 42 decides when the input data are lapped in a temporary memory from an address in a defective map for using on an auxiliary line 38. The data supplied to a display are corrected related to defective line information stored in the memory, and the selected non-committed data driver 36 is a ctivated selectively, and the data signal is provided on the conductive line.

公开(公告)号：JP2005175479A

公开(公告)日：2005-06-30

申请号：JP2004353505

申请日：2004-12-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHEN SHYNG-TSONG ,  CHIRAS STEFANIE R ,  COLBURN MATTHEW EARL ,  DALTON TIMOTHY JOSEPH ,  HEDRICK JEFFREY CURTIS ,  HUANG ELBERT EMIN ,  KUMAR KAUSHIK A ,  LANE MICHAEL WAYNE ,  MALONE KELLY ,  NARAYAN CHANDRASEKHAR ,  NITTA SATYANARAYANA V ,  PURUSHOTHAMAN SAMPATH ,  ROSENBERG ROBERT ,  TYBERG CHRISTY S ,  YU ROY RONGQING

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure which reduces the dielectric constant between conductive lines by providing an air dielectric. SOLUTION: In a multilevel microelectronic integrated circuit, air comprises a permanent line level dielectric, and an ultra-low-k material constitutes a via level dielectric. In the IC structure, air is supplied to the line level after removal of a sacrificial material by clean thermal decomposition and auxiliary diffusion of byproducts through porosities. Optionally, air is also included within porosities in the via level dielectric. By incorporating air into the extension produced in the invention, intralevel and interlevel dielectric values are minimized. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供通过提供空气电介质来降低导线之间的介电常数的结构。 解决方案：在多电平微电子集成电路中，空气包括永久线路电平介质，超低k材料构成通孔级电介质。 在IC结构中，通过清洁的热分解和副产物通过孔隙的辅助扩散除去牺牲材料之后，空气被提供给线路层。 任选地，空气也包括在通孔级电介质中的孔隙中。 通过将空气并入本发明中生产的延伸中，使层内和层间介电值最小化。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2001057085A

公开(公告)日：2001-02-27

申请号：JP2000210249

申请日：2000-07-11

Applicant: IBM

Inventor： KIRIHATA TOSHIAKI ,  DANIEL SUTORASUKA ,  NARAYAN CHANDRASEKHAR ,  WILLIAM TONTEI ,  CLAUDE BARTIN ,  NICK BANHIIRU

IPC: G11C14/00 ,  G11C11/00 ,  G11C16/02 ,  G11C16/04 ,  G11C29/04 ,  H01L21/8246 ,  H01L27/112 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To obtain a partially non-volatile dynamic random access memory(PNDRAM). SOLUTION: A partially non-volatile dynamic random access memory PNDRAM uses a DRAM array formed by plural single transistors 1T cells or two transistors 2T cells. The cell is electrically programmable as a non- volatile memory. Therefore, single chip design characteristic of both of a dynamic random access memory DRAM and an electrically programmable read only memory EPROM can be obtained. A DRAM and an EPROM integrated into a PNDRAM can be always and easily reconstituted during manufacturing or in a market. The PNDRAM has plural applications as a single chip such as a main memory related to ID, BIOS, or operating system information and the like.

公开(公告)号：JP2004193614A

公开(公告)日：2004-07-08

申请号：JP2003409522

申请日：2003-12-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHUDZIK MICHAEL PATRICK ,  DENNARD ROBERT H ,  DIVAKARUNI RAMA ,  FURMAN BRUCE KENNETH ,  JAMMY RAJARAO ,  NARAYAN CHANDRASEKHAR ,  PURUSHOTHAMAN SAMPATH ,  SHEPARD JR JOSEPH F ,  TOPOL ANNA WANDA

IPC: H01L23/12 ,  H01L23/50 ,  H01L25/04 ,  H01L25/18 ,  H01L29/40 ,  H05K1/16 ,  H05K3/46

CPC classification number: H05K1/162 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/30105 ,  H05K1/167 ,  H05K3/4602 ,  H05K2201/09809

Abstract: PROBLEM TO BE SOLVED: To provide a structure for an integrated carrier equipped with high frequency and high speed passive components for computing. SOLUTION: A carrier 200 for a semiconductor component 102 is provided, which has passive components 3010 integrated in its substrate. The passive components 3010 include decoupling components, such as capacitors and resistors. A set of connections 210 is integrated in a close electrical proximity to the supported components. COPYRIGHT: (C)2004,JPO&NCIPI