公开(公告)号：AU2010337304A1

公开(公告)日：2012-07-12

申请号：AU2010337304

申请日：2010-10-27

Applicant: INTEL CORP

Inventor： YAMADA KOICHI ,  SHEAFFER GAD ,  GRAY JAN ,  WANG LANDY ,  TAILLEFER MARTIN ,  KISHAN ARUN ,  ADL-TABATABAI ALI-REZA ,  CALLAHAN DAVID

IPC: G06F9/24 ,  G06F9/30 ,  G06F9/44 ,  G06F13/14

Abstract: In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread. Other embodiments are described and claimed.

公开(公告)号：GB2484416A

公开(公告)日：2012-04-11

申请号：GB201119084

申请日：2009-06-26

Applicant: INTEL CORP

Inventor： SHEAFFER GAD ,  GRAY JAN ,  SMITH BURTON ,  ADL-TABATABAI ALI-REZA ,  GEVA ROBERT ,  BASSIN VADIM ,  CALLAHAN DAVID ,  NI YANG ,  SAHA BRATIN ,  TAILLEFER MARTIN ,  RAIKIN SHLOMO ,  YAMADA KOICHI ,  WANG LANDY ,  KISHAN ARUN

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/10 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109

Abstract: A method and apparatus for optimizing an Unbounded Transactional Memory (UTM) system is herein described. Hardware support for monitors, buffering, and metadata is provided, where orthogonal metaphysical address spaces for metadata may be separate associated with threads and/or software subsystems within threads. In addition, the metadata may be held with hardware in a compressed manner with regard to data transparently to software. Furthermore, in response to metadata access instruction/operations the hardware is capable of supporting a forced metadata value to enable multiple modes of transactional execution. However, if monitors, buffered data, metadata, or other information is lost or conflicts are detected hardware provides for variations of a loss instruction that is able to poll a transaction status register for such loss or conflict and jump execution to a label in response to detecting the loss or conflict. Similarly, multiple variations of a commit instruction are provided for to allow software to define commit conditions and information to clear upon commit. Furthermore, hardware provides support to enable suspension and resume of transactions upon ring level transitions.

公开(公告)号：EP2513783A4

公开(公告)日：2016-12-14

申请号：EP10841429

申请日：2010-10-27

Applicant: INTEL CORP

Inventor： YAMADA KOICHI ,  SHEAFFER GAD ,  GRAY JAN ,  WANG LANDY ,  TAILLEFER MARTIN ,  KISHAN ARUN ,  ADL-TABATABAI ALI-REZA ,  CALLAHAN DAVID

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F9/3834 ,  G06F9/30076 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/461 ,  G06F9/467 ,  G06F9/4812 ,  G06F2209/481

Abstract: A method includes receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread.

公开(公告)号：EP2513803A4

公开(公告)日：2014-02-12

申请号：EP10841434

申请日：2010-11-10

Applicant: INTEL CORP

Inventor： ADL-TABATABAI ALI-REZA ,  SAHA BRATIN ,  BASSIN VADIM ,  SHEAFFER GAD ,  GRAY JAN ,  GROVER VINOD ,  TAILLEFER MARTIN ,  LEVANONI YOSSI ,  DETLEFS DAVE ,  MAGRUDER MIKE ,  TOLTON MATT

IPC: G06F13/14 ,  G06F12/08

CPC classification number: G06F12/0815 ,  G06F9/467 ,  G06F11/141