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    無制限トランザクショナルメモリ（ＵＴＭ）システムの最適化
    1.
    发明专利
    無制限トランザクショナルメモリ（ＵＴＭ）システムの最適化 有权
    优化无限交易记录（UTM）系统

    公开(公告)号：JP2015008008A

    公开(公告)日：2015-01-15

    申请号：JP2014177475

    申请日：2014-09-01

    Applicant: インテル・コーポレーション ,  Intel Corp

    Inventor： GAD SHAEFFER ,  JAN GRAY ,  BURTON SMITH ,  ADL-TABATABAI ALI-REZA ,  ROBERT GEVA ,  VADIM BASSIN ,  DAVID CALLAHAN ,  NI YANG ,  SAHA BRATIN ,  MARTIN TAILLEFER ,  SHLOMO RAIKIN ,  YAMADA KOICHI ,  WANG LANDY ,  ARUN KISHAN

    IPC: G06F12/08

    Abstract: 【課題】無制限トランザクショナルメモリ(UTM)システムを最適化する方法および装置を提供する。【解決手段】キャッシュエントリを保持するデータキャッシュアレイと、データキャッシュアレイに結合されているキャッシュ制御ロジックとを備え、キャッシュ制御ロジックは、キャッシュエントリに対するバッファ済み更新に応じて、キャッシュエントリを、監視されていない状態からバッファ済みコヒーレンシ状態および読出監視状態へと遷移させて、その後に、バッファ済み更新をコミットするためにキャッシュエントリを修正済み状態に遷移させる前に、キャッシュエントリを、バッファ済みコヒーレンシ状態および書込監視状態に遷移させる。【選択図】図1

    Abstract translation: 要解决的问题：提供一种用于优化无限交易内存（UTM）系统的方法和设备。解决方案：该设备包括用于保存高速缓存条目的数据高速缓存阵列和耦合到数据高速缓存阵列的高速缓存控制逻辑，高速缓存 控制逻辑根据高速缓存条目的缓冲更新将缓存条目从非监视状态转移到缓冲的一致性状态和读取监视状态，之后，将高速缓存条目转换为缓冲的一致性状态和写入监视状态 之后将高速缓存条目转换到用于提交缓冲更新的校正状态。

    Optimizations for an unbounded transactional memory (UTM) system
    6.
    发明专利
    Optimizations for an unbounded transactional memory (UTM) system 未知

    公开(公告)号：GB2519877A

    公开(公告)日：2015-05-06

    申请号：GB201500492

    申请日：2009-06-26

    Applicant: INTEL CORP

    Inventor： SHEAFFER GAD ,  GRAY JAN ,  SMITH BURTON ,  ADL-TABATABAI ALI-REZA ,  GEVA ROBERT ,  BASSIN VADIM ,  CALLAHAN DAVID ,  NI YANG ,  SAHA BRATIN ,  TAILLEFER MARTIN ,  RAIKIN SHLOMO ,  YAMADA KOICHI ,  WANG LANDY ,  KISHAN ARUN

    IPC: G06F9/30 ,  G06F9/318 ,  G06F12/10

    Abstract: Disclosed is a apparatus with logic that decodes metadata access instructions, the instructions referencing the data address of a data item, and metadata logic that translates the data address to a distinct metadata address. Metadata logic also accesses the metadata referenced by the distinct metadata address in response to the decoding logic decoding the metadata instruction. Also disclosed is a program that responsive to a data access operation, which references a data address, generates a metadata access operation to reference the data address of the data address operation. The metadata access operation translating the data address to a disjoint metadata address, and accessing the metadata for the data item at the data address based on the metadata address. The metadata access instruction may be a metadata bit test and set instruction, metadata store and set instruction, a metadata store and reset instruction, a compressed metadata test instruction, a compressed metadata store instruction or a compresses metadata clear instruction.

    Optimizations for an unbounded transactional memory (utm) system
    9.
    发明专利
    Optimizations for an unbounded transactional memory (utm) system 未知

    公开(公告)号：GB2484416A

    公开(公告)日：2012-04-11

    申请号：GB201119084

    申请日：2009-06-26

    Applicant: INTEL CORP

    Inventor： SHEAFFER GAD ,  GRAY JAN ,  SMITH BURTON ,  ADL-TABATABAI ALI-REZA ,  GEVA ROBERT ,  BASSIN VADIM ,  CALLAHAN DAVID ,  NI YANG ,  SAHA BRATIN ,  TAILLEFER MARTIN ,  RAIKIN SHLOMO ,  YAMADA KOICHI ,  WANG LANDY ,  KISHAN ARUN

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/10 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109

    Abstract: A method and apparatus for optimizing an Unbounded Transactional Memory (UTM) system is herein described. Hardware support for monitors, buffering, and metadata is provided, where orthogonal metaphysical address spaces for metadata may be separate associated with threads and/or software subsystems within threads. In addition, the metadata may be held with hardware in a compressed manner with regard to data transparently to software. Furthermore, in response to metadata access instruction/operations the hardware is capable of supporting a forced metadata value to enable multiple modes of transactional execution. However, if monitors, buffered data, metadata, or other information is lost or conflicts are detected hardware provides for variations of a loss instruction that is able to poll a transaction status register for such loss or conflict and jump execution to a label in response to detecting the loss or conflict. Similarly, multiple variations of a commit instruction are provided for to allow software to define commit conditions and information to clear upon commit. Furthermore, hardware provides support to enable suspension and resume of transactions upon ring level transitions.

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