公开(公告)号：AU2010337318B2

公开(公告)日：2016-02-18

申请号：AU2010337318

申请日：2010-11-10

Applicant: INTEL CORP

Inventor： ADL-TABATABAI ALI-REZA ,  NI YANG ,  SAHA BRATIN ,  CALLAHAN DAVID ,  BASSIN VADIM ,  SHEAFFER GAD

IPC: G06F3/06 ,  G06F9/06 ,  G06F9/22 ,  G06F9/46

Abstract: In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.

公开(公告)号：WO2011081718A2

公开(公告)日：2011-07-07

申请号：PCT/US2010056142

申请日：2010-11-10

Applicant: INTEL CORP ,  ADL-TABATABAI ALI-REZA ,  NI YANG ,  SAHA BRATIN ,  CALLAHAN DAVID ,  BASSIN VADIM ,  SHEAFFER GAD

Inventor： ADL-TABATABAI ALI-REZA ,  NI YANG ,  SAHA BRATIN ,  CALLAHAN DAVID ,  BASSIN VADIM ,  SHEAFFER GAD

IPC: G06F9/06 ,  G06F3/06 ,  G06F9/22 ,  G06F9/46

CPC classification number: G06F12/0811 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/466 ,  G06F9/467 ,  G06F9/52 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/1027 ,  G06F2212/621

Abstract: In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在第一线程中执行事务存储器（TM）事务，缓冲处理器的高速缓冲存储器的第一缓冲器中的数据块以及获取块上的写监控器以 在更新第一缓冲器中的块的位置处的数据的相遇时间处获得该块的所有权。 描述并要求保护其他实施例。

公开(公告)号：WO2011081704A3

公开(公告)日：2011-08-18

申请号：PCT/US2010054219

申请日：2010-10-27

Applicant: INTEL CORP ,  YAMADA KOICHI ,  SHEAFFER GAD ,  GRAY JAN ,  WANG LANDY ,  TAILLEFER MARTIN ,  KISHAN ARUN ,  ADL-TABATABAI ALI-REZA ,  CALLAHAN DAVID

Inventor： YAMADA KOICHI ,  SHEAFFER GAD ,  GRAY JAN ,  WANG LANDY ,  TAILLEFER MARTIN ,  KISHAN ARUN ,  ADL-TABATABAI ALI-REZA ,  CALLAHAN DAVID

IPC: G06F9/44 ,  G06F9/24 ,  G06F9/30 ,  G06F13/14

CPC classification number: G06F9/3834 ,  G06F9/30076 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/461 ,  G06F9/467 ,  G06F9/4812 ,  G06F2209/481

Abstract: In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在执行无界事务存储器（UTM）事务期间经由来自用户线程的环过渡来以内核模式接收控制的方法，更新与事务状态寄存器（TSR）相关联的状态 用户线程并将TSR与用户线程的上下文一起存储，并且稍后在从内核模式到用户线程的转换期间恢复上下文。 通过这种方式，UTM事务可以继续恢复用户线程。 描述并要求保护其他实施例。

公开(公告)号：BRPI0925055A2

公开(公告)日：2015-07-28

申请号：BRPI0925055

申请日：2009-06-26

Applicant: INTEL CORP

Inventor： SHEAFFER GAD ,  GRAY JAN ,  SMITH BURTON ,  ADL-TABATABAI ALI-REZA ,  GEVA ROBERT ,  BASSIN VADIM ,  CALLAHAN DAVID ,  NI YANG ,  SAHA BRATIN ,  TAILLEFER MARTIN ,  RAIKIN SHLOMO ,  YAMADA KOICHI ,  WANG LANDY ,  KISHAN ARUN

IPC: G06F9/06 ,  G06F9/44 ,  G06F9/46 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109 ,  G06F13/00 ,  G06F15/00

公开(公告)号：DE112009005006T5

公开(公告)日：2013-01-10

申请号：DE112009005006

申请日：2009-06-26

Applicant: INTEL CORP

Inventor： SHEAFFER GAD ,  GRAY JAN ,  SMITH BURTON ,  GEVA ROBERT ,  BASSIN VADIM ,  CALLAHAN DAVID ,  NI YANG ,  SAHA BRATIN ,  TAILLEFER MARTIN ,  RAIKIN SHLOMO ,  KISHAN ARUN ,  ADL-TABATABAI ALI-REZA ,  WANG LANDY ,  YAMADA KOICHI

IPC: G06F9/06 ,  G06F9/44 ,  G06F9/46 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109 ,  G06F13/00 ,  G06F15/00

Abstract: Ein Verfahren und eine Vorrichtung zum Optimieren eines unbounded transactional memory (UTM) Systems werden hierin beschrieben. Eine Hardware-Unterstützung für Monitore, Puffer und Metadaten wird bereitgestellt, wobei orthogonale metaphysikalische Adressräume für Metadaten getrennt mit Threads und/oder Software-Untersystemen innerhalb von Threads verbunden werden können. Zusätzlich können die Metadaten durch Hardware in einer komprimierten Weise hinsichtlich für Software transparenten Daten gehalten werden. Darüber hinaus ist die Hardware in Reaktion auf eine Metadatenzugriffsinstruktion/Operationen in der Lage, einen erzwungenen Metadatenwert zu unterstützen, um mehrere Modi einer transaktionalen Ausführung freizugeben. Falls jedoch Monitore, gepufferte Daten, Metadaten oder andere Informationen verlorengehen oder Konflikte erfasst werden, sorgt die Hardware für Variationen einer Verlustinstruktion, die in der Lage ist, ein Transaktionsstaturregister für einen derartigen Verlust oder Konflikt zu pollen und die Ausführung zu einer Marke in Reaktion auf das Erfassen des Verlustes oder Konflikts zu springen. In ähnlicher Weise werden mehrere Variationen einer Commit-Instruktion bereitgestellt, um es Software zu ermöglichen, Commit-Bedingungen und Informationen zum Löschen bei einem Commit zu definieren. Darüber hinaus liefert die Hardware eine Unterstützung, um eine Aussetzung und Wiederaufnahme von Transaktionen bei Ringniveauübergängen zu ermöglichen.

公开(公告)号：AU2010337304B2

公开(公告)日：2016-02-04

申请号：AU2010337304

申请日：2010-10-27

Applicant: INTEL CORP

Inventor： YAMADA KOICHI ,  SHEAFFER GAD ,  GRAY JAN ,  WANG LANDY ,  TAILLEFER MARTIN ,  KISHAN ARUN ,  ADL-TABATABAI ALI-REZA ,  CALLAHAN DAVID

IPC: G06F9/24 ,  G06F9/30 ,  G06F9/44 ,  G06F13/14

Abstract: In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread. Other embodiments are described and claimed.

公开(公告)号：GB2519877B

公开(公告)日：2015-07-29

申请号：GB201500492

申请日：2009-06-26

Applicant: INTEL CORP

Inventor： SHEAFFER GAD ,  GRAY JAN ,  SMITH BURTON ,  ADL-TABATABAI ALI-REZA ,  GEVA ROBERT ,  BASSIN VADIM ,  CALLAHAN DAVID ,  NI YANG ,  SAHA BRATIN ,  TAILLEFER MARTIN ,  RAIKIN SHLOMO ,  YAMADA KOICHI ,  WANG LANDY ,  KISHAN ARUN

IPC: G06F9/30 ,  G06F9/318 ,  G06F12/10

公开(公告)号：EP2513779A4

公开(公告)日：2014-01-29

申请号：EP10841433

申请日：2010-11-10

Applicant: INTEL CORP

Inventor： ADL-TABATABAI ALI-REZA ,  NI YANG ,  SAHA BRATIN ,  CALLAHAN DAVID ,  BASSIN VADIM ,  SHEAFFER GAD

IPC: G06F9/06 ,  G06F3/06 ,  G06F9/22 ,  G06F9/46

CPC classification number: G06F12/0811 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/466 ,  G06F9/467 ,  G06F9/52 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/1027 ,  G06F2212/621

Abstract: In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.

公开(公告)号：EP2513783A4

公开(公告)日：2016-12-14

申请号：EP10841429

申请日：2010-10-27

Applicant: INTEL CORP

Inventor： YAMADA KOICHI ,  SHEAFFER GAD ,  GRAY JAN ,  WANG LANDY ,  TAILLEFER MARTIN ,  KISHAN ARUN ,  ADL-TABATABAI ALI-REZA ,  CALLAHAN DAVID

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F9/3834 ,  G06F9/30076 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/461 ,  G06F9/467 ,  G06F9/4812 ,  G06F2209/481

Abstract: A method includes receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread.

公开(公告)号：GB2519877A

公开(公告)日：2015-05-06

申请号：GB201500492

申请日：2009-06-26

Applicant: INTEL CORP

Inventor： SHEAFFER GAD ,  GRAY JAN ,  SMITH BURTON ,  ADL-TABATABAI ALI-REZA ,  GEVA ROBERT ,  BASSIN VADIM ,  CALLAHAN DAVID ,  NI YANG ,  SAHA BRATIN ,  TAILLEFER MARTIN ,  RAIKIN SHLOMO ,  YAMADA KOICHI ,  WANG LANDY ,  KISHAN ARUN

IPC: G06F9/30 ,  G06F9/318 ,  G06F12/10

Abstract: Disclosed is a apparatus with logic that decodes metadata access instructions, the instructions referencing the data address of a data item, and metadata logic that translates the data address to a distinct metadata address. Metadata logic also accesses the metadata referenced by the distinct metadata address in response to the decoding logic decoding the metadata instruction. Also disclosed is a program that responsive to a data access operation, which references a data address, generates a metadata access operation to reference the data address of the data address operation. The metadata access operation translating the data address to a disjoint metadata address, and accessing the metadata for the data item at the data address based on the metadata address. The metadata access instruction may be a metadata bit test and set instruction, metadata store and set instruction, a metadata store and reset instruction, a compressed metadata test instruction, a compressed metadata store instruction or a compresses metadata clear instruction.