公开(公告)号：AU2010337319A1

公开(公告)日：2012-07-12

申请号：AU2010337319

申请日：2010-11-10

Applicant: INTEL CORP

Inventor： ADL-TABATABAI ALI-REZA ,  SAHA BRATIN ,  BASSIN VADIM ,  SHEAFFER GAD ,  GRAY JAN ,  GROVER VINOD ,  TAILLEFER MARTIN ,  LEVANONI YOSSI ,  DETLEFS DAVE ,  MAGRUDER MIKE ,  TOLTON MATT

IPC: G06F12/08 ,  G06F13/14

Abstract: In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed.

公开(公告)号：WO2011081704A3

公开(公告)日：2011-08-18

申请号：PCT/US2010054219

申请日：2010-10-27

Applicant: INTEL CORP ,  YAMADA KOICHI ,  SHEAFFER GAD ,  GRAY JAN ,  WANG LANDY ,  TAILLEFER MARTIN ,  KISHAN ARUN ,  ADL-TABATABAI ALI-REZA ,  CALLAHAN DAVID

Inventor： YAMADA KOICHI ,  SHEAFFER GAD ,  GRAY JAN ,  WANG LANDY ,  TAILLEFER MARTIN ,  KISHAN ARUN ,  ADL-TABATABAI ALI-REZA ,  CALLAHAN DAVID

IPC: G06F9/44 ,  G06F9/24 ,  G06F9/30 ,  G06F13/14

CPC classification number: G06F9/3834 ,  G06F9/30076 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/461 ,  G06F9/467 ,  G06F9/4812 ,  G06F2209/481

Abstract: In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在执行无界事务存储器（UTM）事务期间经由来自用户线程的环过渡来以内核模式接收控制的方法，更新与事务状态寄存器（TSR）相关联的状态 用户线程并将TSR与用户线程的上下文一起存储，并且稍后在从内核模式到用户线程的转换期间恢复上下文。 通过这种方式，UTM事务可以继续恢复用户线程。 描述并要求保护其他实施例。

公开(公告)号：AU2010337319B2

公开(公告)日：2016-02-04

申请号：AU2010337319

申请日：2010-11-10

Applicant: INTEL CORP

Inventor： ADL-TABATABAI ALI-REZA ,  SAHA BRATIN ,  BASSIN VADIM ,  SHEAFFER GAD ,  GRAY JAN ,  GROVER VINOD ,  TAILLEFER MARTIN ,  LEVANONI YOSSI ,  DETLEFS DAVE ,  MAGRUDER MIKE ,  TOLTON MATT

IPC: G06F12/08 ,  G06F13/14

Abstract: In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed.

公开(公告)号：BRPI0925055A2

公开(公告)日：2015-07-28

申请号：BRPI0925055

申请日：2009-06-26

Applicant: INTEL CORP

Inventor： SHEAFFER GAD ,  GRAY JAN ,  SMITH BURTON ,  ADL-TABATABAI ALI-REZA ,  GEVA ROBERT ,  BASSIN VADIM ,  CALLAHAN DAVID ,  NI YANG ,  SAHA BRATIN ,  TAILLEFER MARTIN ,  RAIKIN SHLOMO ,  YAMADA KOICHI ,  WANG LANDY ,  KISHAN ARUN

IPC: G06F9/06 ,  G06F9/44 ,  G06F9/46 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109 ,  G06F13/00 ,  G06F15/00

公开(公告)号：DE112009005006T5

公开(公告)日：2013-01-10

申请号：DE112009005006

申请日：2009-06-26

Applicant: INTEL CORP

Inventor： SHEAFFER GAD ,  GRAY JAN ,  SMITH BURTON ,  GEVA ROBERT ,  BASSIN VADIM ,  CALLAHAN DAVID ,  NI YANG ,  SAHA BRATIN ,  TAILLEFER MARTIN ,  RAIKIN SHLOMO ,  KISHAN ARUN ,  ADL-TABATABAI ALI-REZA ,  WANG LANDY ,  YAMADA KOICHI

IPC: G06F9/06 ,  G06F9/44 ,  G06F9/46 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109 ,  G06F13/00 ,  G06F15/00

Abstract: Ein Verfahren und eine Vorrichtung zum Optimieren eines unbounded transactional memory (UTM) Systems werden hierin beschrieben. Eine Hardware-Unterstützung für Monitore, Puffer und Metadaten wird bereitgestellt, wobei orthogonale metaphysikalische Adressräume für Metadaten getrennt mit Threads und/oder Software-Untersystemen innerhalb von Threads verbunden werden können. Zusätzlich können die Metadaten durch Hardware in einer komprimierten Weise hinsichtlich für Software transparenten Daten gehalten werden. Darüber hinaus ist die Hardware in Reaktion auf eine Metadatenzugriffsinstruktion/Operationen in der Lage, einen erzwungenen Metadatenwert zu unterstützen, um mehrere Modi einer transaktionalen Ausführung freizugeben. Falls jedoch Monitore, gepufferte Daten, Metadaten oder andere Informationen verlorengehen oder Konflikte erfasst werden, sorgt die Hardware für Variationen einer Verlustinstruktion, die in der Lage ist, ein Transaktionsstaturregister für einen derartigen Verlust oder Konflikt zu pollen und die Ausführung zu einer Marke in Reaktion auf das Erfassen des Verlustes oder Konflikts zu springen. In ähnlicher Weise werden mehrere Variationen einer Commit-Instruktion bereitgestellt, um es Software zu ermöglichen, Commit-Bedingungen und Informationen zum Löschen bei einem Commit zu definieren. Darüber hinaus liefert die Hardware eine Unterstützung, um eine Aussetzung und Wiederaufnahme von Transaktionen bei Ringniveauübergängen zu ermöglichen.

公开(公告)号：WO2011081719A3

公开(公告)日：2011-11-24

申请号：PCT/US2010056172

申请日：2010-11-10

Applicant: INTEL CORP ,  ADL-TABATABAI ALI-REZA ,  SAHA BRATIN ,  BASSIN VADIM ,  SHEAFFER GAD ,  GRAY JAN ,  GROVER VINOD ,  TAILLEFER MARTIN ,  LEVANONI YOSSI ,  DETLEFS DAVE ,  MAGRUDER MIKE ,  TOLTON MATT

Inventor： ADL-TABATABAI ALI-REZA ,  SAHA BRATIN ,  BASSIN VADIM ,  SHEAFFER GAD ,  GRAY JAN ,  GROVER VINOD ,  TAILLEFER MARTIN ,  LEVANONI YOSSI ,  DETLEFS DAVE ,  MAGRUDER MIKE ,  TOLTON MATT

IPC: G06F13/14 ,  G06F12/08

CPC classification number: G06F12/0815 ,  G06F9/467 ,  G06F11/141

Abstract: In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在具有多个事务执行模式的无界事务存储器（UTM）系统中选择开始第一事务的第一事务执行模式的方法。 这些事务执行模式包括在处理器的高速缓冲存储器内执行的硬件模式，使用处理器的事务硬件执行的硬件辅助模式以及软件缓冲器，以及在没有事务性硬件的情况下执行的软件事务存储器（STM）模式。 如果在STM模式下没有执行等待事务，则可以将第一事务执行模式选择为硬件模式的最高执行模式，否则可以选择较低的执行模式。 描述和要求保护其他实施例。

公开(公告)号：GB2519877A

公开(公告)日：2015-05-06

申请号：GB201500492

申请日：2009-06-26

Applicant: INTEL CORP

Inventor： SHEAFFER GAD ,  GRAY JAN ,  SMITH BURTON ,  ADL-TABATABAI ALI-REZA ,  GEVA ROBERT ,  BASSIN VADIM ,  CALLAHAN DAVID ,  NI YANG ,  SAHA BRATIN ,  TAILLEFER MARTIN ,  RAIKIN SHLOMO ,  YAMADA KOICHI ,  WANG LANDY ,  KISHAN ARUN

IPC: G06F9/30 ,  G06F9/318 ,  G06F12/10

Abstract: Disclosed is a apparatus with logic that decodes metadata access instructions, the instructions referencing the data address of a data item, and metadata logic that translates the data address to a distinct metadata address. Metadata logic also accesses the metadata referenced by the distinct metadata address in response to the decoding logic decoding the metadata instruction. Also disclosed is a program that responsive to a data access operation, which references a data address, generates a metadata access operation to reference the data address of the data address operation. The metadata access operation translating the data address to a disjoint metadata address, and accessing the metadata for the data item at the data address based on the metadata address. The metadata access instruction may be a metadata bit test and set instruction, metadata store and set instruction, a metadata store and reset instruction, a compressed metadata test instruction, a compressed metadata store instruction or a compresses metadata clear instruction.

公开(公告)号：GB2484416B

公开(公告)日：2015-02-25

申请号：GB201119084

申请日：2009-06-26

Applicant: INTEL CORP

Inventor： SHEAFFER GAD ,  GRAY JAN ,  SMITH BURTON ,  ADL-TABATABAI ALI-REZA ,  GEVA ROBERT ,  BASSIN VADIM ,  CALLAHAN DAVID ,  NI YANG ,  SAHA BRATIN ,  TAILLEFER MARTIN ,  RAIKIN SHLOMO ,  YAMADA KOICHI ,  WANG LANDY ,  KISHAN ARUN

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/10 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109

公开(公告)号：AU2010337304A1

公开(公告)日：2012-07-12

申请号：AU2010337304

申请日：2010-10-27

Applicant: INTEL CORP

Inventor： YAMADA KOICHI ,  SHEAFFER GAD ,  GRAY JAN ,  WANG LANDY ,  TAILLEFER MARTIN ,  KISHAN ARUN ,  ADL-TABATABAI ALI-REZA ,  CALLAHAN DAVID

IPC: G06F9/24 ,  G06F9/30 ,  G06F9/44 ,  G06F13/14

Abstract: In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread. Other embodiments are described and claimed.

公开(公告)号：GB2484416A

公开(公告)日：2012-04-11

申请号：GB201119084

申请日：2009-06-26

Applicant: INTEL CORP

Inventor： SHEAFFER GAD ,  GRAY JAN ,  SMITH BURTON ,  ADL-TABATABAI ALI-REZA ,  GEVA ROBERT ,  BASSIN VADIM ,  CALLAHAN DAVID ,  NI YANG ,  SAHA BRATIN ,  TAILLEFER MARTIN ,  RAIKIN SHLOMO ,  YAMADA KOICHI ,  WANG LANDY ,  KISHAN ARUN

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/10 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109

Abstract: A method and apparatus for optimizing an Unbounded Transactional Memory (UTM) system is herein described. Hardware support for monitors, buffering, and metadata is provided, where orthogonal metaphysical address spaces for metadata may be separate associated with threads and/or software subsystems within threads. In addition, the metadata may be held with hardware in a compressed manner with regard to data transparently to software. Furthermore, in response to metadata access instruction/operations the hardware is capable of supporting a forced metadata value to enable multiple modes of transactional execution. However, if monitors, buffered data, metadata, or other information is lost or conflicts are detected hardware provides for variations of a loss instruction that is able to poll a transaction status register for such loss or conflict and jump execution to a label in response to detecting the loss or conflict. Similarly, multiple variations of a commit instruction are provided for to allow software to define commit conditions and information to clear upon commit. Furthermore, hardware provides support to enable suspension and resume of transactions upon ring level transitions.