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    METHOD AND APPARATUS FOR ENABLING A LOW POWER MODE FOR A PROCESSOR
    12.
    发明申请
    METHOD AND APPARATUS FOR ENABLING A LOW POWER MODE FOR A PROCESSOR 审中-公开
    为处理器启用低功耗模式的方法和装置

    公开(公告)号：WO03054675A2

    公开(公告)日：2003-07-03

    申请号：PCT/US0240706

    申请日：2002-12-18

    Applicant: INTEL CORP

    Inventor： MITTAL MILLIND ,  HORIGAN JOHN ,  DAI XIA ,  CLINE LESLIE

    IPC: G06F1/32 ,  G06F12/08

    CPC classification number: G06F1/3203 ,  G06F12/0891

    Abstract: In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicate the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.

    Abstract translation: 根据本发明的实施例，启动触发事件以将处理器置于低功率状态。 根据电源状态信号，处理器可能进入或不进入低功率状态时刷新高速缓存。 功率状态信号可以指示与将处理器置于低功率状态相关联的功率降低的相对优先级，而不首先冲洗高速缓存，而与高功率状态中的电压降低相关联的高速缓存中的软错误率的增加。

    A METHOD AND APPARATUS FOR EXECUTING FLOATING POINT AND PACKED DATA INSTRUCTIONS USING A SINGLE REGISTER FILE
    15.
    发明公开
    A METHOD AND APPARATUS FOR EXECUTING FLOATING POINT AND PACKED DATA INSTRUCTIONS USING A SINGLE REGISTER FILE 失效
    方法和设备实施GLUTKOMMA-和紧凑型数据的指令与单个寄存器集合

    公开(公告)号：EP0868689A4

    公开(公告)日：2000-02-16

    申请号：EP96944983

    申请日：1996-12-17

    Applicant: INTEL CORP

    Inventor： LIN DERRICK ,  VAKKALAGADDA RAMAMOHAN R ,  GLEW ANDREW F ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BISTRY DAVID ,  MITTAL MILLIND ,  DULONG CAROLE ,  KOWASHI EIICHI ,  EITAN BENNY

    IPC: G06F7/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48

    CPC classification number: G06F9/30123 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30134 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

    Abstract: A method and apparatus for executing floating point and packed data instructions using a single physical register file that is aliased. According to one aspect of the invention, processor is provided that includes a decode unit (1002), a mapping unit (1004), and a storage unit (1006). The decode unit (1002) is configured to decode instructions and their operands from at least one instruction set including at least a first and second set of instructions. The storage unit (1006) includes a physical register file (1020). The mapping unit (1004) is configured to map operands used by the first set of instructions to the physical register file in a stock referenced manner. In addition, the mapping unit (1004) is configured to map operands used by the second set of instructions to the same physical register file in a non-stack reference manner.

    Abstract translation: 一种用于执行浮点和紧缩数据说明，用一个单一的物理寄存器文件的方法和装置也被混叠。 。根据本发明的一个方面，提供了一种处理器做包括一解码单元，映射单元，以及存储单元。 解码单元被配置为指令和其操作数从至少一个指令集包括至少一个第一和第二组指令进行解码。 所述存储单元包括一个物理寄存器文件。 所述映射单元被配置为在一个股票引用方式使用由第一组的说明将物理寄存器文件的操作数。 另外，映射单元被配置成映射在一个非堆叠参考方式使用由所述第二组指令到相同的物理寄存器堆的操作数。

    MICROPROCESSOR WITH COMPARE OPERATION OF COMPOSITE OPERANDS
    16.
    发明公开
    MICROPROCESSOR WITH COMPARE OPERATION OF COMPOSITE OPERANDS 失效
    WITH比较操作复合操作数微处理器

    公开(公告)号：EP0795154A4

    公开(公告)日：1999-03-10

    申请号：EP95943654

    申请日：1995-12-01

    Applicant: INTEL CORP

    Inventor： PELEG ALEXANDER ,  YAARI YAAKOV ,  MITTAL MILLIND ,  MENNEMEIER LARRY M ,  EITAN BENNY

    IPC: G06F7/02 ,  G06F9/30 ,  G06F9/302 ,  G06F7/20

    CPC classification number: G06F9/30014 ,  G06F7/026 ,  G06F9/30021 ,  G06F9/30036 ,  G06F2207/3828

    Abstract: A processor includes a decoder (202) coupled to receive a control signal (207). The control signal has a first source address (602), a second source address (603), a destination address (605), and an operation field (601). The first source address corresponds to a first location, and the second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data compare operation is to be performed. The processor includes a circuit coupled to the decoder for comparing a first packed data being stored at the first location with a second packed data being stored at the second location and for communicating a corresponding result packed data to the third location.

    LOCALIZED PERFORMANCE THROTTLING TO REDUCE IC POWER CONSUMPTION
    17.
    发明公开
    LOCALIZED PERFORMANCE THROTTLING TO REDUCE IC POWER CONSUMPTION 失效
    当地的电力控制来降低集成电路的能耗

    公开(公告)号：EP1023656A4

    公开(公告)日：2002-07-03

    申请号：EP97944556

    申请日：1997-09-29

    Applicant: INTEL CORP

    Inventor： MITTAL MILLIND ,  VALENTINE ROBERT

    IPC: G06F1/32

    CPC classification number: G06F9/3842 ,  G06F1/32 ,  G06F9/3001 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3857

    Abstract: The power consumed within an integrated circuit (IC) is reduced by throttling the performance of particular functional units (105) within the IC. The recent utilization levels of particular functional units within an IC are monitored (108), for example, by computing each functional unit's average duty cycle over its recent operating history (106). If this activity level (109) is greater than a threshold, the functional unit is operated in a reduced-power mode (110). The threshold value is set large enough to allow short bursts of high utilization to occur. An IC can dynamically make the tradeoff between high-speed operation and low-power operation, by throttling back performance of functional units when their utilization exceeds a sustainable level. This dynamic power/speed tradeoff can be optimized across multiple functional units within an IC or among multiple ICs within a system. This dynamic power/speed tradeoff can be altered by providing software control over throttling parameters.

    A SYSTEM FOR SIGNAL PROCESSING USING MULTIPLY-ADD OPERATIONS
    19.
    发明公开
    A SYSTEM FOR SIGNAL PROCESSING USING MULTIPLY-ADD OPERATIONS 失效
    与MULTIPLIZIERUNG-信号处理系统添加操作

    公开(公告)号：EP0870224A4

    公开(公告)日：1999-02-10

    申请号：EP96945274

    申请日：1996-12-24

    Applicant: INTEL CORP

    Inventor： DULONG CAROLE ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BUI TUAN H ,  KOWASHI EIICHI ,  MITTAL MILLIND ,  EITAN BENNY ,  FISHER STEPHEN A ,  MAYTAL BENNY

    IPC: G06F7/544 ,  G06F9/302 ,  G06F7/38 ,  G06F7/52 ,  G06F15/00 ,  G06F15/76 ,  G06F15/78 ,  G06F15/80

    CPC classification number: G06F9/30036 ,  G06F7/5443 ,  G06F9/30014 ,  G06F2207/3828

    Abstract: A computer system which includes a multimedia input device which generates an audio or video input signal and a processor coupled to the multimedia input device. The system further includes a storage device coupled to the processor and having stored therein a signal processing routine for multiplying and accumulating input values representative of the audio or video input signal. The signal processing routine, when executed by the processor, causes the processor to perform several steps. These steps include performing a packed multiply add on a first set of values packed into a first source and a second set of values packed into a second source each representing input signals to generate a packed intermediate result. The packed intermediate result is added to an accumulator to generate a packed accumulated result in the accumulator. These steps may be iterated with the first set of values and portions of the second set of values to the accumulator to generate the packed accumulated result. Subsequent thereto, the packed accumulated result in the accumulator is unpacked into a first result and a second result and the first result and the second result are added together to generate an accumulated result.

    CACHE HIERARCHY MANAGEMENT WITH LOCALITY HINTS FOR DIFFERENT CACHE LEVELS
    20.
    发明公开
    CACHE HIERARCHY MANAGEMENT WITH LOCALITY HINTS FOR DIFFERENT CACHE LEVELS 失效
    WITH LOCAL-说明不同级别的内存缓存层次管理

    公开(公告)号：EP1012723A4

    公开(公告)日：2002-11-20

    申请号：EP97953136

    申请日：1997-12-12

    Applicant: INTEL CORP

    Inventor： MITTAL MILLIND

    IPC: G06F12/08 ,  G06F13/00

    CPC classification number: G06F9/30047 ,  G06F12/0888 ,  G06F12/0897

    Abstract: A computer system and method in which allocation of a cache memory (21a, 22a) is managed by utilizing a locality hint value (17, 18), included within an instruction (19), which controls if cache allocation is to be made. The locality value is based on spatial and/or temporal locality for a data access and may be assigned to each level of a cache hierarchy where allocation control is desired. The locality hint value may be used to identify a lowest level where management of cache allocation is desired and cache is allocated at that level and any higher level or levels. If the locality hint identifies a particular access for data as temporal or non-temporal with respect to a particular cache level, the particular access may be determined to be temporal or non-temporal with respect to the higher and lower cache levels.

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