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    HIGH ASPECT RATIO ETCH USING MODULATION OF RF POWERS OF VARIOUS FREQUENCIES
    14.
    发明专利
    HIGH ASPECT RATIO ETCH USING MODULATION OF RF POWERS OF VARIOUS FREQUENCIES 未知

    公开(公告)号：SG130195A1

    公开(公告)日：2007-03-20

    申请号：SG2007009798

    申请日：2004-08-06

    Applicant: LAM RES CORP

    Inventor： RUSU CAMELIA ,  DHINDSA RAJINDER ,  HUDSON ERIC A ,  SRINIVASAN MUKUND ,  LI LUMIN ,  KOZAKEVICH FELIX

    IPC: B23B3/10 ,  H01J37/32 ,  H01L21/311 ,  H01L21/467 ,  H05H1/46

    Abstract: A method for etching a high aspect ratio feature through a mask into a layer to be etched over a substrate is provided. The substrate is place (404) in a process chamber, which is able to provide RF power at a first frequency, a second frequency different than the first frequency, and a third frequency different than the first and second frequency. An etchant gas is provided (408) to the process chamber. A first etch step is provided (412) where the first frequency, the second frequency, and the third frequency are at power settings for the first etch step. A second etch step is provided (416), where the first frequency, the second frequency, and the third frequency are at a different power setting. Optionally, a third etch step may also be provided (420).

    Methods and apparatus for determining an etch endpoint in a plasma processing system
    15.
    发明专利
    Methods and apparatus for determining an etch endpoint in a plasma processing system 未知

    公开(公告)号：AU5925999A

    公开(公告)日：2000-04-17

    申请号：AU5925999

    申请日：1999-09-15

    Applicant: LAM RES CORP

    Inventor： WINNICZEK JAROSLAW W ,  DASSAPA M J FRANCOIS CHANDRASE ,  HUDSON ERIC A ,  WIEPKING MARK

    IPC: H01L21/302 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/66 ,  H01L21/683 ,  H02N13/00 ,  H01L21/68

    Abstract: Methods and apparatus for ascertaining the end of an etch process while etching through a target layer on a substrate in a plasma processing system which employs an electrostatic chuck. The end of the etch process is ascertained by monitoring the electric potential of the substrate to detect a pattern indicative of the end of the etch process. By the way of example, changes to this potential may be observed by monitoring the current flowing to the pole of the electrostatic chuck. Upon ascertaining the pattern indicative of the end of the etch process, for example by monitoring the current signal, a control signal is produced to terminate the etch. If a bias compensation power supply is provided to keep the currents flowing to the poles of the electrostatic chuck substantially equal but opposite in sign throughout the etch, the compensation voltage output by the bias compensation power supply may be monitored for the aforementioned pattern indicative of the end of the etch process in order to terminate the etch.

    SYSTEM, METHOD AND APPARATUS FOR PLASMA ETCH HAVING INDEPENDENT CONTROL OF ION GENERATION AND DISSOCIATION OF PROCESS GAS
    16.
    发明专利
    SYSTEM, METHOD AND APPARATUS FOR PLASMA ETCH HAVING INDEPENDENT CONTROL OF ION GENERATION AND DISSOCIATION OF PROCESS GAS 未知

    公开(公告)号：SG183268A1

    公开(公告)日：2012-09-27

    申请号：SG2012059390

    申请日：2011-01-28

    Applicant: LAM RES CORP

    Inventor： HUDSON ERIC A

    Abstract: A method of etching a semiconductor wafer including injecting a source gas mixture into a process chamber including injecting the source gas mixture into a multiple hollow cathode cavities in a top electrode of the process chamber and generating a plasma in each one of the hollow cathode cavities. Generating the plasma in the hollow cathode cavities includes applying a first biasing signal to the hollow cathode cavities. The generated plasma or activated species is output from corresponding outlets of each of the hollow cathode cavities into a wafer processing region in the process chamber. The wafer processing region Is located between the outlets of the hollow cathode cavities and a surface to be etched. An etchant gas mixture is injected into the wafer processing region. A plasma can also be supported and/or generated in the wafer processing region.

    METHOD FOR FORMING SELF-ALIGNED CONTACTS/ VIAS WITH HIGH CORNER SELECTIVITY
    18.
    发明专利
    METHOD FOR FORMING SELF-ALIGNED CONTACTS/ VIAS WITH HIGH CORNER SELECTIVITY 未知

    公开(公告)号：SG10201805023PA

    公开(公告)日：2018-07-30

    申请号：SG10201805023P

    申请日：2014-12-03

    Applicant: LAM RES CORP

    Inventor： INDRAKANTI ANANTH ,  WANG PENG ,  HUDSON ERIC A

    Abstract: OF THE DISCLOSURE METHOD FOR FORMING SELF 唰ALIGNED CONTACTS/ VIAS 研'1TH HIGH CORNER SELECTIVITY A method of etching self-aligned contact/via features in a low-k dielectric layer disposed below a hardmask, which is disposed below a planarizatio 丑 layer. At least one cycle is provided, where each cycle comprises thinning the planarization layer, forming a deposition layer on the hardmask and planarization layer; and etching the low去 dielectric 10 layer masked by the deposition layer. FIG. 1 2 0

    METHOD FOR FORMING SELF-ALIGNED CONTACTS/ VIAS WITH HIGH CORNER SELECTIVITY
    19.
    发明专利
    METHOD FOR FORMING SELF-ALIGNED CONTACTS/ VIAS WITH HIGH CORNER SELECTIVITY 未知

    公开(公告)号：SG10201408046TA

    公开(公告)日：2015-07-30

    申请号：SG10201408046T

    申请日：2014-12-03

    Applicant: LAM RES CORP

    Inventor： INDRAKANTI ANANTH ,  WANG PENG ,  HUDSON ERIC A

    Abstract: A method of etching self-aligned contact/via features in a low-k dielectric layer disposed below a hardmask, which is disposed below a planarization layer. At least one cycle is provided, where each cycle comprises thinning the planarization layer, forming a deposition layer on the hardmask and planarization layer; and etching the low-k dielectric layer masked by the deposition layer.

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