公开(公告)号：WO2005022623B1

公开(公告)日：2005-05-26

申请号：PCT/US2004025406

申请日：2004-08-06

Applicant: LAM RES CORP ,  RUSU CAMELIA ,  DHINDSA RAJINDER ,  HUDSON ERIC A ,  SRINIVASAN MUKUND ,  LI LUMIN ,  KOZAKEVICH FELIX

Inventor： RUSU CAMELIA ,  DHINDSA RAJINDER ,  HUDSON ERIC A ,  SRINIVASAN MUKUND ,  LI LUMIN ,  KOZAKEVICH FELIX

IPC: B23B3/10 ,  H01J37/32 ,  H01L21/311 ,  H01L21/467 ,  H05H1/46

CPC classification number: H01J37/32165 ,  H01J37/32082 ,  H01J37/32155 ,  H01J2237/3347 ,  H01L21/31116 ,  H01L21/67063 ,  H01L21/67069

Abstract: A method for etching a high aspect ratio feature through a mask into a layer to be etched over a substrate is provided. The substrate is placed (404) in a process chamber, which is able to provide RF power at a first frequency, a second frequency different than the first frequency, and a third frequency different than the first and second frequency. An etchant gas is provided (408) to the process chamber. A first etch step is provided (412) where the first frequency, the second frequency, and the third frequency are at power settings for the first etch step. A second etch step is provided (416), where the first frequency, the second frequency, and the third frequency are at a different power setting. Optionally, a third etch step may also be provided (420).

Abstract translation: 提供了一种通过掩模将高宽比特征蚀刻到衬底上待蚀刻的层中的方法。 衬底被放置在处理室中，处理室能够提供第一频率的RF功率，不同于第一频率的第二频率以及不同于第一和第二频率的第三频率。 向处理室提供蚀刻剂气体（408）。 提供第一蚀刻步骤（412），其中第一频率，第二频率和第三频率处于第一蚀刻步骤的功率设置。 提供第二蚀刻步骤（416），其中第一频率，第二频率和第三频率处于不同的功率设置。 可选地，还可以提供第三蚀刻步骤（420）。

公开(公告)号：EP1656694A4

公开(公告)日：2009-11-11

申请号：EP04780271

申请日：2004-08-06

Applicant: LAM RES CORP

Inventor： RUSU CAMELIA ,  DHINDSA RAJINDER ,  HUDSON ERIC A ,  SRINIVASAN MUKUND ,  LI LUMIN ,  KOZAKEVICH FELIX

IPC: H01L21/00 ,  B23B3/10 ,  H01J37/32 ,  H01L21/306 ,  H01L21/311 ,  H01L21/467 ,  H05H1/46

CPC classification number: H01J37/32165 ,  H01J37/32082 ,  H01J37/32155 ,  H01J2237/3347 ,  H01L21/31116 ,  H01L21/67063 ,  H01L21/67069

公开(公告)号：EP1661171A4

公开(公告)日：2009-03-11

申请号：EP04781695

申请日：2004-08-20

Applicant: LAM RES CORP

Inventor： DHINDSA RAJINDER ,  SADJADI REZA S M ,  KOZAKEVICH FELIX ,  TRUSSELL DAVE ,  LI LUMIN ,  LENZ ERIC ,  RUSU CAMELIA ,  SRINIVASAN MUKUND ,  EPPLER AARON ,  TIETZ JIM ,  MARKS JEFFREY

IPC: H01J37/32 ,  B23B3/10 ,  H01L21/311 ,  H01L21/467 ,  H05H1/46

CPC classification number: H01J37/32174 ,  H01J37/32082 ,  H01J37/32165

Abstract: A workpiece (18) is processed with a plasma (8) in a vacuum plasma processing chamber (10) by exciting the plasma at several frequencies (51, 52, 54, 56, 58), such that the excitation of the plasma by the several frequencies simultaneously causes several different phenomena to occur in the plasma. The chamber includes top central (14, 36, 36a) and bottom electrodes (13, 16) and a peripheral top (42) and/or bottom electrode (34) arrangement that is either powered by RF or is connected to a reference potential by a filter arrangement that passes at least one of the plasma excitation ftequencies to the exclusion of other frequencies. Controller 24 is employed to direct parameter control of various motors (M), valves (V), frequencies (58), power (59), temperature control means (25, 45) and set points (50).

公开(公告)号：WO2007040958A2

公开(公告)日：2007-04-12

申请号：PCT/US2006036110

申请日：2006-09-15

Applicant: LAM RES CORP ,  DHINDSA RAJINDER ,  LENZ ERIC ,  LI LUMIN ,  KOZAKEVICH FELIX

Inventor： DHINDSA RAJINDER ,  LENZ ERIC ,  LI LUMIN ,  KOZAKEVICH FELIX

IPC: H01T23/00

CPC classification number: H01L21/6833 ,  H02N13/00

Abstract: An electrostatic chuck assembly having a dielectric material and/or having a cavity with varying thickness, profile and/or shape is disclosed. The electrostatic chuck assembly includes a conductive support and an electrostatic chuck ceramic layer. A dielectric layer or insert is located between the conductive support and an electrostatic chuck ceramic layer. A cavity can be located in a seating surface of the electrostatic chuck ceramic layer. An embedded pole pattern can be optionally incorporated in the electrostatic chuck assembly. Methods of manufacturing the electrostatic chuck assembly are disclosed as are methods to improve the uniformity of a flux field above a workpiece during a plasma processing process.

Abstract translation: 公开了具有介电材料和/或具有变化的厚度，型材和/或形状的空腔的静电卡盘组件。 静电卡盘组件包括导电支架和静电卡盘陶瓷层。 电介质层或插入件位于导电支架和静电卡盘陶瓷层之间。 空腔可以位于静电卡盘陶瓷层的就座表面中。 嵌入式极图可以可选地并入静电卡盘组件中。 公开了制造静电卡盘组件的方法，是在等离子体处理过程中改进工件上方的磁通场的均匀性的方法。

公开(公告)号：WO2005020264A2

公开(公告)日：2005-03-03

申请号：PCT/US2004027064

申请日：2004-08-20

Applicant: LAM RES CORP ,  DHINDSA RAJINDER ,  SADJADI REZA S M ,  KOZAKEVICH FELIX ,  TRUSSELL DAVE ,  LI LUMIN ,  LENZ ERIC ,  RUSU CAMELIA ,  SRINIVASAN MUKUND ,  EPPLER AARON ,  TIETZ JIM ,  MARKS JEFFREY

Inventor： DHINDSA RAJINDER ,  SADJADI REZA S M ,  KOZAKEVICH FELIX ,  TRUSSELL DAVE ,  LI LUMIN ,  LENZ ERIC ,  RUSU CAMELIA ,  SRINIVASAN MUKUND ,  EPPLER AARON ,  TIETZ JIM ,  MARKS JEFFREY

IPC: H01J37/32 ,  H01J

CPC classification number: H01J37/32174 ,  H01J37/32082 ,  H01J37/32165

Abstract: A workpiece is processed with a plasma in a vacuum plasma processing chamber by exciting the plasma at several frequencies such that the excitation of the plasma by the several frequencies simultaneously causes several different phenomena to occur in the plasma. The chamber includes central top and bottom electrodes and a peripheral top and/or bottom electrode arrangement that is either powered by RF or is connected to a reference potential by a filter arrangement that passes at least one of the plasma excitation ftequencies to the exclusion of other frequencies.

Abstract translation: 通过以几个频率激发等离子体，在真空等离子体处理室中用等离子体处理工件，使得等离子体被几个频率激发同时导致在等离子体中发生几种不同的现象。 腔室包括中心顶部和底部电极以及由RF供电的外围顶部和/或底部电极装置，或者通过将至少一个等离子体激发频率传递到排除另一个等离子体激发频率的滤波器装置连接到参考电位 频率。

公开(公告)号：WO9910923B1

公开(公告)日：1999-05-14

申请号：PCT/US9817607

申请日：1998-08-25

Applicant: LAM RES CORP

Inventor： ZHU HELEN H ,  MUELLER GEORGE A ,  NGUYEN THOMAS D ,  LI LUMIN

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311

CPC classification number: H01L21/31116

Abstract: Disclosed is a method for improving the selectivity of dielectric layers to photoresist layers and base layers. The method is performed in a plasma processing chamber, and the photoresist layer is coated over the dielectric layer. The method includes introducing an etchant source gas into the plasma processing chamber, which consists essentially of a CxFy gas and an N2 gas. The method further includes striking a plasma in the plasma processing chamber from the etchant source gas. The method additionally includes etching at least a portion of the dielectric layer with the plasma through to a base layer that underlies the dielectric layer. The method is also well suited for anisotropically etching an oxide layer with very high selectivities to Si, Si3N4, TiN, and metal silicides.

Abstract translation: 公开了一种用于改善电介质层对光致抗蚀剂层和基层的选择性的方法。 该方法在等离子体处理室中执行，并且光致抗蚀剂层被涂覆在介电层上。 该方法包括将蚀刻剂源气体引入等离子体处理室，该等离子体处理室基本上由CxFy气体和N 2气体组成。 该方法还包括在等离子体处理室中从蚀刻剂源气体中打出等离子体。 该方法另外包括用等离子体将至少一部分介电层蚀刻到位于介电层下面的基底层。 该方法也非常适合于对Si，Si 3 N 4，TiN和金属硅化物具有非常高的选择性的各向异性蚀刻氧化物层。

公开(公告)号：WO2009099769A3

公开(公告)日：2009-10-15

申请号：PCT/US2009031713

申请日：2009-01-22

Applicant: LAM RES CORP ,  SADJADI S M REZA ,  LI LUMIN ,  ROMANO ANDREW R

Inventor： SADJADI S M REZA ,  LI LUMIN ,  ROMANO ANDREW R

IPC: H01L21/027

CPC classification number: H01L21/0337

Abstract: A method for providing features in an etch layer is provided by forming an organic mask layer over the inorganic mask layer, forming a silicon-containing mask layer over the organic mask layer, forming a patterned mask layer over the silicon-containing mask layer, etching the silicon-containing mask layer through the patterned mask, depositing a polymer over the etched silicon-containing mask layer, depositing a silicon-containing film over the polymer, planarizing the silicon-containing film, selectively removing the polymer leaving the silicon-containing film, etching the organic layer, and etching the inorganic layer.

Abstract translation: 通过在无机掩模层上形成有机掩模层，在有机掩模层上形成含硅掩模层，在含硅掩模层上形成图案化掩模层，蚀刻，提供蚀刻层中提供特征的方法 通过图案化掩模的含硅掩模层，在蚀刻的含硅掩模层上沉积聚合物，在聚合物上沉积含硅膜，平坦化含硅膜，选择性地除去离开含硅膜的聚合物 蚀刻有机层，并蚀刻无机层。

公开(公告)号：WO2007078572A3

公开(公告)日：2009-02-05

申请号：PCT/US2006046780

申请日：2006-12-08

Applicant: LAM RES CORP ,  DHINDSA RAJINDER ,  KOZAKEVICH FELIX ,  LI LUMIN ,  TRUSSELL DAVE

Inventor： DHINDSA RAJINDER ,  KOZAKEVICH FELIX ,  LI LUMIN ,  TRUSSELL DAVE

IPC: H01L21/683

CPC classification number: H01J37/32082 ,  H01J37/32174

Abstract: A number of RF power transmission paths are defined to extend from an RF power source through a matching network, through a transmit electrode, through a plasma to a number of return electrodes. A number of tuning elements are respectively disposed within the number of RF power transmission paths. Each tuning element is defined to adjust an amount of RF power to be transmitted through the RF power transmission path within which the tuning element is disposed. A plasma density within a vicinity of a particular RF power transmission path is directly proportional to the amount of RF power transmitted through the particular RF power transmission path. Therefore, adjustment of RF power transmitted through the RF power transmission paths, as afforded by the tuning element, enables control of a plasma density profile across a substrate.

Abstract translation: 多个RF功率传输路径被定义为从RF电源通过匹配网络，通过发射电极，等离子体延伸到多个返回电极。 多个调谐元件分别设置在RF功率传输路径的数量内。 每个调谐元件被定义为调整要通过设置调谐元件的RF功率传输路径传输的RF功率的量。 特定RF功率传输路径附近的等离子体密度与通过特定RF功率传输路径传输的RF功率的量成正比。 因此，由调谐元件提供的通过RF功率传输路径传输的RF功率的调整能够控制跨越衬底的等离子体密度分布。

公开(公告)号：WO0039837A8

公开(公告)日：2001-08-30

申请号：PCT/US9930739

申请日：1999-12-22

Applicant: LAM RES CORP

Inventor： LI LUMIN ,  MUELLER GEORGE

IPC: H05H1/46 ,  H01J37/32 ,  H01L21/302 ,  H01L21/3065

CPC classification number: H01J37/32623 ,  H01J37/32165 ,  Y10S156/915

Abstract: The invention relates to a plasma processing reactor apparatus for semiconductor processing a substrate. The apparatus includes a chamber. The apparatus further includes a top electrode configured to be coupled to a first RF power source having a first RF frequency and a bottom electrode configured to be coupled to second RF power source having a second RF frequency that is lower than the first RF frequency. The apparatus additionally includes an insulating shroud that lines an interior of the chamber, the insulating shroud being configured to be electrically floating during the processing. The apparatus further includes a perforated plasma confinement ring disposed outside of an outer periphery of the bottom electrode, a top surface of the perforated plasma confinement ring being disposed below a top surface of the substrate and electrically grounded during the processing.

Abstract translation: 本发明涉及用于半导体处理衬底的等离子体处理反应器装置。 该装置包括一个室。 该装置还包括被配置为耦合到具有第一RF频率的第一RF电源的顶部电极和配置成耦合到具有低于第一RF频率的第二RF频率的第二RF电源的底部电极。 该装置还包括绝缘护罩，其在腔室的内部排列，绝缘护罩被配置为在处理期间电浮动。 所述设备还包括设置在所述底部电极的外周的外侧的穿孔等离子体限制环，所述多孔等离子体限制环的顶表面设置在所述基板的顶表面下方并且在所述加工期间电接地。

公开(公告)号：WO9966533A9

公开(公告)日：2001-05-31

申请号：PCT/US9913474

申请日：1999-06-15

Applicant: LAM RES CORP

Inventor： KUTHI ANDRAS ,  LI LUMIN

IPC: H05H1/46 ,  H01J37/32 ,  H01L21/302 ,  H01L21/3065

CPC classification number: H01J37/32009 ,  H01J37/32082 ,  H01J37/3244 ,  H01J37/32541

Abstract: Disclosed is a system for processing a semiconductor wafer through plasma etching operations. The system has a process chamber that includes a support chuck for holding the semiconductor wafer and a pair of RF power sources. In another case, the system can be configured such that the electrode is grounded and the pair of RF frequencies are fed to the support chuck (bottom electrode). The system therefore includes an electrode that is positioned within the system and over the semiconductor wafer. The electrode has a center region, a first surface and a second surface. The first surface is configured to receive processing gases from a source that is external to the system and flow the processing gases into the center region. The second surface has a plurality of gas feed holes that are continuously coupled to a corresponding plurality of electrode openings that have electrode opening diameters that are greater than gas feed hole diameters of the plurality of gas feed holes. The plurality of electrode openings are configured to define an electrode surface that is defined over a wafer surface of the semiconductor wafer. The electrode surface assists in increasing an electrode plasma sheath area in order to cause a shift in bias voltage onto the wafer surface, thereby increasing the ion bombardment energy over the wafer without increasing the plasma density.

Abstract translation: 公开了一种通过等离子体蚀刻操作来处理半导体晶片的系统。 该系统具有包括用于保持半导体晶片和一对RF电源的支撑卡盘的处理室。 在另一种情况下，可以将系统配置为使得电极接地，并将一对RF频率馈送到支撑卡盘（底部电极）。 因此，该系统包括位于系统内并在半导体晶片之上的电极。 电极具有中心区域，第一表面和第二表面。 第一表面被配置为从系统外部的源接收处理气体并将处理气体流入中心区域。 第二表面具有多个气体供给孔，其连续地耦合到具有大于多个气体供给孔的气体供给孔直径的电极开口直径的对应的多个电极开口。 多个电极开口被配置为限定限定在半导体晶片的晶片表面上的电极表面。 电极表面有助于增加电极等离子体鞘的面积，以便使晶片表面上的偏置电压发生偏移，从而增加晶片上的离子轰击能量而不增加等离子体密度。