11.
    发明专利
    未知

    公开(公告)号:DE69808020T2

    公开(公告)日:2003-05-22

    申请号:DE69808020

    申请日:1998-10-14

    Abstract: A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.

    12.
    发明专利
    未知

    公开(公告)号:AT224558T

    公开(公告)日:2002-10-15

    申请号:AT98119388

    申请日:1998-10-14

    Abstract: A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.

    MICROCONTROLLER WITH INTERNAL CLOCK FOR LIQUID CRYSTAL DISPLAY
    13.
    发明公开
    MICROCONTROLLER WITH INTERNAL CLOCK FOR LIQUID CRYSTAL DISPLAY 失效
    与内部时钟发生器液晶显示单片机

    公开(公告)号:EP0852790A4

    公开(公告)日:1999-10-27

    申请号:EP97933156

    申请日:1997-06-26

    CPC classification number: G06F1/3265 G06F1/3203 G09G3/18 Y02D10/153

    Abstract: A device including a microcontroller fabricated on a semiconductor chip is used to control an LCD display of an external system intended to be controlled by the microcontroller. The microcontroller enters a sleep state in which it operates in a battery power conservation mode during periods of time when functional activity of the microcontroller is reduced. The microcontroller awakens from the sleep state for resumption of activity when such a period ends. Timing to the LCD is decoupled from the microcontroller's own internal clock when the independent internal on-chip clock, which may be an RC oscillator, is selected by the user of the device. This allows the chip to continue to drive the LCD display even though the microcontroller's internal clock has stopped during the sleep.

    MICROCONTROLLER WITH LIQUID CRYSTAL DISPLAY CHARGE PUMP
    14.
    发明公开
    MICROCONTROLLER WITH LIQUID CRYSTAL DISPLAY CHARGE PUMP 失效
    带液晶显示电荷泵微控制器

    公开(公告)号:EP0847572A4

    公开(公告)日:1999-10-20

    申请号:EP97931321

    申请日:1997-06-26

    Abstract: A microcontroller (50) chip (51) includes a charge pump with a switched-capacitor (83) that develops a plurality of discrete voltages. A switched-capacitor (83) charging circuit selectively charges a capacitor to produce successive charges individually retrievable from the capacitor. An LCD driver (173) selectively transmits the discrete operating voltage levels to activate the LCD (10) according to status of an external system under the control of the microcontroller (50). Voltage losses that may occur during the switched-capacitor (83) charging are compensated to maintain the levels of the discrete operating voltages free of decay. Compensation is achieved by overcharging the capacitor (83) by an amount substantially equivalent to the amount of voltage loss on the capacitor, using active feedback obtained from monitoring the charge on the capacitor.

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