DATA POINTER TO OUTPUT INDIRECT ADDRESSING MODE ADDRESS WITHIN SINGLE CYCLE AND ITS METHOD

    公开(公告)号:JPH11232100A

    公开(公告)日:1999-08-27

    申请号:JP30756298

    申请日:1998-10-28

    Abstract: PROBLEM TO BE SOLVED: To generate an indirect addressing mode address by providing a multiplexer circuit connected to the respective output terminals of a data pointer register, an incrementer and an adder. SOLUTION: A data pointer register 12 stores the current address of an operand used in a simple indirect addressing mode. An incrementer 14 increases the current address of the operand stored in the data pointer register 12. An adder 16 adds the current address and an offset value stored in the data pointer register 12. A multiplexer circuit 18 having a first input terminal connected to the output terminal of the data pointer register 12, a second input terminal connected to the output terminal of the incrementer 14 and a third input terminal connected to the output terminal of the adder 16 selects a desired generated indirect addressing mode address and outputs the selected address to an instruction register.

    2.
    发明专利
    未知

    公开(公告)号:DE69808020T2

    公开(公告)日:2003-05-22

    申请号:DE69808020

    申请日:1998-10-14

    Abstract: A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.

    3.
    发明专利
    未知

    公开(公告)号:AT224558T

    公开(公告)日:2002-10-15

    申请号:AT98119388

    申请日:1998-10-14

    Abstract: A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.

    4.
    发明专利
    未知

    公开(公告)号:AT522860T

    公开(公告)日:2011-09-15

    申请号:AT00915025

    申请日:2000-03-23

    Abstract: A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is possible through register files or data memory. Special function registers, including the Program Counter (PC) and Working Register (W), are mapped in the data memory. An orthogonal (symmetrical) instruction set makes possible any operation on any register using any addressing mode. Consequently, two file registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the W register. Thus increasing performance and decreasing program memory usage.

    5.
    发明专利
    未知

    公开(公告)号:DE69808020D1

    公开(公告)日:2002-10-24

    申请号:DE69808020

    申请日:1998-10-14

    Abstract: A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.

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