12.
    发明专利
    未知

    公开(公告)号:DE60128608T2

    公开(公告)日:2008-01-31

    申请号:DE60128608

    申请日:2001-01-24

    Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

    15.
    发明专利
    未知

    公开(公告)号:DE69701176T2

    公开(公告)日:2000-06-15

    申请号:DE69701176

    申请日:1997-09-11

    Abstract: The device includes a control circuit (CC) with n primary circuits (CE1,CEn), each representing a critical; path of an electronic circuit to be monitored. Each primary circuit delivers a control signal (POR1,.. PORn) which is then transmitted to a logical gate OR. A common signal (POR) is generated by the gate. A voltage detector (DET) delivers a temperature independent signal (TPOR) to the other input of the logical gate. The signal TPOR has an amplitude equal to the threshold voltage (Vs) of the device.

    17.
    发明专利
    未知

    公开(公告)号:DE602006010452D1

    公开(公告)日:2009-12-31

    申请号:DE602006010452

    申请日:2006-02-07

    Abstract: The circuit has a linear regulator (4`) for supplying a DC supply voltage (Vdd) to an internal load (29) from an external voltage (Vps). Chopper type capacitive clipping supply circuits (5), with switched capacitances, are in parallel with the activated linear regulator. The circuits supply current at the same time as the linear regulator, during an operation phase (D) of the integrated circuit which corresponds to a phase in which a calculating processor which contains the internal load is active.. An independent claim is also included for a method for scrambling the current signature of a load including an integrated circuit.

    18.
    发明专利
    未知

    公开(公告)号:DE60128314T2

    公开(公告)日:2008-01-17

    申请号:DE60128314

    申请日:2001-11-12

    Abstract: Random signal generator comprises an MOS transistor as an electronic noise source. The MOS transistor is operated with a drain source current having a random component and has means for producing a binary random signal from the random drain source current. The current channel is arranged to be curved or S shaped by suitable doping. The invention also relates to an integrated circuit with a binary signal generator based on an MOS transistor. The circuit has suitable connections for connecting to other circuits. An Independent claim is made for a method for generating a random signal from an electronic noise source, in which an MOS transistor with an S or screw shaped channel is used.

    DETECTEUR DE PICS PARASITES DANS L'ALIMENTATION D'UN CIRCUIT INTEGRE

    公开(公告)号:FR2895115A1

    公开(公告)日:2007-06-22

    申请号:FR0553962

    申请日:2005-12-20

    Abstract: L'invention concerne un circuit de détection de pics parasites sur l'alimentation d'un circuit électronique, comportant au moins un premier transistor (MP51) dont la borne de commande est reliée à une borne (52) d'application d'un premier potentiel d'une tension d'alimentation (Vcc) du circuit et dont une première borne de conduction est reliée à une borne (52) d'application d'un deuxième potentiel (Vcc) par l'intermédiaire d'au moins un premier élément résistif (R1), la deuxième borne de conduction du premier transistor fournissant le résultat (Vd) de la détection.

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