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公开(公告)号：FR2788616B1
公开(公告)日：2001-04-20
申请号：FR9900472
申请日：1999-01-15
Applicant: ST MICROELECTRONICS SA
Inventor： ROMAIN FABRICE , MONIER GUY , LEPAREUX MARIE NOELLE
Abstract: The multiplier circuit forms part of a mathematical generator assembly and has three input adders (14-17) series cascade connected with bistable connection circuits (7-9) and with bistable input connections (10-13). There is a nulling circuit (18) which prevents the operation of the input and output two bistable circuits (10,13) allowing operation within the mathematical generator assembly.
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公开(公告)号：FR2923923A1
公开(公告)日：2009-05-22
申请号：FR0759136
申请日：2007-11-19
Applicant: ST MICROELECTRONICS SA , PROTON WORLD INT NV
Inventor： ROMAIN FABRICE , MODAVE JEAN LOUIS
Abstract: L'invention concerne un procédé et un circuit de vérification de données transférées entre un circuit (21) et une unité de traitement (11), dans lequel : les données provenant du circuit transitent par un premier élément de mémorisation temporaire (23) ayant une taille multiple de la taille de données susceptibles d'être présentées ensuite sur un bus (27) de l'unité de traitement ; une adresse fournie par l'unité de traitement (11) à destination du circuit est stockée temporairement dans un deuxième élément (22) ; et le contenu du premier élément est comparé avec une donnée courante (CDATA) provenant du circuit, au moins lorsqu'elle correspond à une adresse d'une donnée déjà présente dans ce premier élément.
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公开(公告)号：DE60220793T2
公开(公告)日：2008-03-06
申请号：DE60220793
申请日：2002-04-29
Applicant: ST MICROELECTRONICS SA
Inventor： LIARDET PIERRE-YVAN , ROMAIN FABRICE
Abstract: The invention concerns a method for encrypting, with a random quantity (r), a calculation using at least a modular operation (3), the method consisting in multiplying a first modulo (n) by said random quantity, in taking as modulo of the operation, the result (m) of said multiplication and in carrying out a modular reduction of the result of the operation, on the basis of the first modulo (n).
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公开(公告)号：DE60220793D1
公开(公告)日：2007-08-02
申请号：DE60220793
申请日：2002-04-29
Applicant: ST MICROELECTRONICS SA
Inventor： LIARDET PIERRE-YVAN , ROMAIN FABRICE
Abstract: The invention concerns a method for encrypting, with a random quantity (r), a calculation using at least a modular operation (3), the method consisting in multiplying a first modulo (n) by said random quantity, in taking as modulo of the operation, the result (m) of said multiplication and in carrying out a modular reduction of the result of the operation, on the basis of the first modulo (n).
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公开(公告)号：DE60314055D1
公开(公告)日：2007-07-12
申请号：DE60314055
申请日：2003-07-02
Applicant: ST MICROELECTRONICS SA
Inventor： LIARDET PIERRE-YVAN , ROMAIN FABRICE , TEGLIA YANNICK , SIRTORI LAURENCE
IPC: H04L9/06
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Patent Agency Ranking
公开(公告)号：FR2790347B1
公开(公告)日：2001-10-05
申请号：FR9902364
申请日：1999-02-25
Applicant: ST MICROELECTRONICS SA
Inventor： ROMAIN FABRICE
Abstract: A method for providing security to a chaining of useful operations of the same type, performed by an electronic circuit executing an algorithm, randomly introduces one or more dummy operations in the chaining of operations. This prevents any fraudulent access to protected data through a statistical analysis of electrical currents.
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公开(公告)号：FR2790345B1
公开(公告)日：2001-04-27
申请号：FR9902365
申请日：1999-02-25
Applicant: ST MICROELECTRONICS SA
Inventor： LIARDET PIERRE YVAN , ROMAIN FABRICE , PLESSIER BERNARD , HENNEBOIS BRIGITTE
Abstract: The secure coprocessor encryption technique has a memory module (30) and a battery of input/output registers (32). A multiplexer (34) transfers the digital words between the input/output register and the input register (36). There is a key register (38) and processing module (42). The battery of input/output registers has an external noise interference register (50) showing when the encryption/de encryption and digital key are at risk.
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公开(公告)号：FR2790345A1
公开(公告)日：2000-09-01
申请号：FR9902365
申请日：1999-02-25
Applicant: ST MICROELECTRONICS SA
Inventor： LIARDET PIERRE YVAN , ROMAIN FABRICE , PLESSIER BERNARD , HENNEBOIS BRIGITTE
Abstract: The secure coprocessor encryption technique has a memory module (30) and a battery of input/output registers (32). A multiplexer (34) transfers the digital words between the input/output register and the input register (36). There is a key register (38) and processing module (42). The battery of input/output registers has an external noise interference register (50) showing when the encryption/de encryption and digital key are at risk.
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公开(公告)号：FR2788616A1
公开(公告)日：2000-07-21
申请号：FR9900472
申请日：1999-01-15
Applicant: ST MICROELECTRONICS SA
Inventor： ROMAIN FABRICE , MONIER GUY , LEPAREUX MARIE NOELLE
Abstract: The multiplier circuit forms part of a mathematical generator assembly and has three input adders (14-17) series cascade connected with bistable connection circuits (7-9) and with bistable input connections (10-13). There is a nulling circuit (18) which prevents the operation of the input and output two bistable circuits (10,13) allowing operation within the mathematical generator assembly.
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公开(公告)号：DE602006014753D1
公开(公告)日：2010-07-22
申请号：DE602006014753
申请日：2006-04-11
Applicant: ST MICROELECTRONICS SA
Inventor： ROMAIN FABRICE , POMET ALAIN
IPC: G06K19/073 , G06F21/75 , G06F21/77 , G06F21/79 , G07F7/10
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