公开(公告)号：DE69739825D1

公开(公告)日：2010-05-12

申请号：DE69739825

申请日：1997-09-24

Applicant: ST MICROELECTRONICS SRL

Inventor： BARTOLI SIMONE ,  DIMA VINCENZO ,  SALI MAURO LUIGI

IPC: G11C8/00 ,  G11C8/12 ,  G11C16/06 ,  G11C16/08

公开(公告)号：IT1314122B1

公开(公告)日：2002-12-04

申请号：ITMI992576

申请日：1999-12-13

Applicant: ST MICROELECTRONICS SRL

Inventor： DIMA VINCENZO ,  BEDARIDA LORENZO ,  GERACI ANTONINO ,  BARTOLI SIMONE

IPC: G05F3/24

Abstract: An output buffer device having first and second supply voltage references, the first voltage reference being lower in value than the second voltage reference. The output buffer device includes first and second complementary MOS transistors, which transistors are connected in series together between one of the supply voltage references and a further voltage reference, have gate terminals connected together and to an input terminal of this buffer device, and have drain terminals connected together and to an output terminal of the buffer device. Advantageously, the first transistor is connected to the first supply voltage reference. Furthermore, the output buffer device comprises at least one additional drive MOS transistor of the same type as the first MOS transistor and placed between the second supply voltage reference and the output terminal of the buffer device.

公开(公告)号：DE69620855T2

公开(公告)日：2002-11-21

申请号：DE69620855

申请日：1996-06-20

Applicant: ST MICROELECTRONICS SRL

Inventor： VILLA CORRADO ,  BETTINI LUIGI ,  BARTOLI SIMONE

IPC: H03K17/693

公开(公告)号：ITMI992372D0

公开(公告)日：1999-11-12

申请号：ITMI992372

申请日：1999-11-12

Applicant: ST MICROELECTRONICS SRL

Inventor： BEDARIDA LORENZO ,  BARTOLI SIMONE ,  SALI MAURO ,  RUSSO ANTONIO

IPC: G11C5/14 ,  G11C8/12 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30

公开(公告)号：DE69628402D1

公开(公告)日：2003-07-03

申请号：DE69628402

申请日：1996-06-20

Applicant: ST MICROELECTRONICS SRL

Inventor： TASSAN CASER FABIO ,  VILLA CORRADO ,  BARTOLI SIMONE

IPC: G11C5/14 ,  G11C16/06

公开(公告)号：DE69620855D1

公开(公告)日：2002-05-29

申请号：DE69620855

申请日：1996-06-20

Applicant: ST MICROELECTRONICS SRL

Inventor： VILLA CORRADO ,  BETTINI LUIGI ,  BARTOLI SIMONE

IPC: H03K17/693

公开(公告)号：ITMI992576A1

公开(公告)日：2001-06-13

申请号：ITMI992576

申请日：1999-12-13

Applicant: ST MICROELECTRONICS SRL

Inventor： BEDARIDA LORENZO ,  BARTOLI SIMONE ,  DIMA VINCENZO ,  GERACI ANTONINO

IPC: G05F3/24

Abstract: An output buffer device having first and second supply voltage references, the first voltage reference being lower in value than the second voltage reference. The output buffer device includes first and second complementary MOS transistors, which transistors are connected in series together between one of the supply voltage references and a further voltage reference, have gate terminals connected together and to an input terminal of this buffer device, and have drain terminals connected together and to an output terminal of the buffer device. Advantageously, the first transistor is connected to the first supply voltage reference. Furthermore, the output buffer device comprises at least one additional drive MOS transistor of the same type as the first MOS transistor and placed between the second supply voltage reference and the output terminal of the buffer device.

公开(公告)号：ITMI992372A1

公开(公告)日：2001-05-14

申请号：ITMI992372

申请日：1999-11-12

Applicant: ST MICROELECTRONICS SRL

Inventor： BEDARIDA LORENZO ,  BARTOLI SIMONE ,  SALI MAURO ,  RUSSO ANTONIO

IPC: G11C5/14 ,  G11C8/12 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30

公开(公告)号：ITMI992576D0

公开(公告)日：1999-12-13

申请号：ITMI992576

申请日：1999-12-13

Applicant: ST MICROELECTRONICS SRL

Inventor： BEDARIDA LORENZO ,  BARTOLI SIMONE ,  DIMA VINCENZO ,  GERACI ANTONINO

IPC: G05F3/24

Abstract: An output buffer device having first and second supply voltage references, the first voltage reference being lower in value than the second voltage reference. The output buffer device includes first and second complementary MOS transistors, which transistors are connected in series together between one of the supply voltage references and a further voltage reference, have gate terminals connected together and to an input terminal of this buffer device, and have drain terminals connected together and to an output terminal of the buffer device. Advantageously, the first transistor is connected to the first supply voltage reference. Furthermore, the output buffer device comprises at least one additional drive MOS transistor of the same type as the first MOS transistor and placed between the second supply voltage reference and the output terminal of the buffer device.

公开(公告)号：DE69940369D1

公开(公告)日：2009-03-19

申请号：DE69940369

申请日：1999-11-25

Applicant: ST MICROELECTRONICS SRL

Inventor： BARTOLI SIMONE ,  GERACI ANTONINO ,  SALI MAURO ,  BEDARIDA LORENZO

IPC: G11C7/00 ,  G11C7/10

Abstract: The invention relates to a read control circuit portion (1) and an attendant reading method for an electronic memory device (2) integrated in a semiconductor and including a non-volatile memory matrix (4) with associated row and column decoders (5,6) connected to respective outputs of an address counter (7), an ATD circuit (12) for detecting an input transaction as the memory device is being accessed, and read amplifiers (8) and attendant registers (10) for transferring the data read from the memory (2) to the output. The control circuit portion (1) comprises a detection circuit block (15) which is input a clock signal (CK) and a logic signal (BAN) to enable reading in the burst mode, and a burst read mode control logic (3) connected downstream of the circuit block (15). The method of this invention comprises accessing the memory matrix in a random read mode; detecting a request for access in the burst read mode; and executing the parallel reading of a plurality of memory words during a single period of time clocked by a clock signal (CK).