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    1.
    发明专利
    未知

    公开(公告)号：DE69940369D1

    公开(公告)日：2009-03-19

    申请号：DE69940369

    申请日：1999-11-25

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BARTOLI SIMONE ,  GERACI ANTONINO ,  SALI MAURO ,  BEDARIDA LORENZO

    IPC: G11C7/00 ,  G11C7/10

    Abstract: The invention relates to a read control circuit portion (1) and an attendant reading method for an electronic memory device (2) integrated in a semiconductor and including a non-volatile memory matrix (4) with associated row and column decoders (5,6) connected to respective outputs of an address counter (7), an ATD circuit (12) for detecting an input transaction as the memory device is being accessed, and read amplifiers (8) and attendant registers (10) for transferring the data read from the memory (2) to the output. The control circuit portion (1) comprises a detection circuit block (15) which is input a clock signal (CK) and a logic signal (BAN) to enable reading in the burst mode, and a burst read mode control logic (3) connected downstream of the circuit block (15). The method of this invention comprises accessing the memory matrix in a random read mode; detecting a request for access in the burst read mode; and executing the parallel reading of a plurality of memory words during a single period of time clocked by a clock signal (CK).

    4.
    发明专利
    未知

    公开(公告)号：ITMI20001315A1

    公开(公告)日：2001-12-13

    申请号：ITMI20001315

    申请日：2000-06-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BEDARIDA LORENZO ,  GERACI ANTONINO ,  LISI CARLO ,  DIMA VINCENZO

    IPC: G11C16/28

    Abstract: The present invention relates a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor comprising a mirror transistor, a first transistor and a second transistor, said mirror transistor and said first transistor having in common the gate electrodes in a circuit node, said second transistor being connected in a transdiode configuration and placed between the gate electrode and the drain electrode of said first transistor, and a current source being connected to the gate electrode of said first transistor and to the drain electrode of said second transistor, characterized by comprising a third transistor which is configured to receive a switching signal at its gate electrode and is connected between the drain and the gate electrode of said first transistor.

    5.
    发明专利
    未知

    公开(公告)号：ITMI992576A1

    公开(公告)日：2001-06-13

    申请号：ITMI992576

    申请日：1999-12-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BEDARIDA LORENZO ,  BARTOLI SIMONE ,  DIMA VINCENZO ,  GERACI ANTONINO

    IPC: G05F3/24

    Abstract: An output buffer device having first and second supply voltage references, the first voltage reference being lower in value than the second voltage reference. The output buffer device includes first and second complementary MOS transistors, which transistors are connected in series together between one of the supply voltage references and a further voltage reference, have gate terminals connected together and to an input terminal of this buffer device, and have drain terminals connected together and to an output terminal of the buffer device. Advantageously, the first transistor is connected to the first supply voltage reference. Furthermore, the output buffer device comprises at least one additional drive MOS transistor of the same type as the first MOS transistor and placed between the second supply voltage reference and the output terminal of the buffer device.

    6.
    发明专利
    未知

    公开(公告)号：ITMI992576D0

    公开(公告)日：1999-12-13

    申请号：ITMI992576

    申请日：1999-12-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BEDARIDA LORENZO ,  BARTOLI SIMONE ,  DIMA VINCENZO ,  GERACI ANTONINO

    IPC: G05F3/24

    Abstract: An output buffer device having first and second supply voltage references, the first voltage reference being lower in value than the second voltage reference. The output buffer device includes first and second complementary MOS transistors, which transistors are connected in series together between one of the supply voltage references and a further voltage reference, have gate terminals connected together and to an input terminal of this buffer device, and have drain terminals connected together and to an output terminal of the buffer device. Advantageously, the first transistor is connected to the first supply voltage reference. Furthermore, the output buffer device comprises at least one additional drive MOS transistor of the same type as the first MOS transistor and placed between the second supply voltage reference and the output terminal of the buffer device.

    7.
    发明专利
    未知

    公开(公告)号：DE60041056D1

    公开(公告)日：2009-01-22

    申请号：DE60041056

    申请日：2000-08-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GERACI ANTONINO ,  LISI CARLO ,  BEDARIDA LORENZO ,  SFORZIN MARCO

    IPC: G11C16/28 ,  G11C7/12

    Abstract: A direct-comparison reading circuit for a nonvolatile memory array (2) having a plurality of memory cells (4) arranged in rows and columns (9), and at least one bit line (7), includes at least one array line (13), selectively connectable to the bit line (7), and a reference line (14); a precharging circuit (17) for precharging the array line (13) and reference line (14) at a preset precharging potential (VPC); at least one comparator (35) having a first terminal connected to the array line (13), and a second terminal connected to the reference line (14); and an equalization circuit (15, 23, 26) for equalizing the potentials of the array line (13) and reference line (14) in the precharging step. In addition, the reading circuit includes an equalization line (15) distinct from the reference line (14); and controlled switches (23, 26) for connecting, in the precharging step, the equalization line (15) to the array line (13) and to the reference line (14), and for disconnecting the equalization line (15) from the array line (13) and from the reference line (14) at the end of the precharging step.

    8.
    发明专利
    未知

    公开(公告)号：ITMI20001315D0

    公开(公告)日：2000-06-13

    申请号：ITMI20001315

    申请日：2000-06-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BEDARIDA LORENZO ,  GERACI ANTONINO ,  LISI CARLO ,  DIMA VINCENZO

    IPC: G11C16/28

    Abstract: The present invention relates a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor comprising a mirror transistor, a first transistor and a second transistor, said mirror transistor and said first transistor having in common the gate electrodes in a circuit node, said second transistor being connected in a transdiode configuration and placed between the gate electrode and the drain electrode of said first transistor, and a current source being connected to the gate electrode of said first transistor and to the drain electrode of said second transistor, characterized by comprising a third transistor which is configured to receive a switching signal at its gate electrode and is connected between the drain and the gate electrode of said first transistor.

    9.
    发明专利
    未知

    公开(公告)号：IT1318013B1

    公开(公告)日：2003-07-21

    申请号：ITMI20001315

    申请日：2000-06-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： LISI CARLO ,  BEDARIDA LORENZO ,  GERACI ANTONINO ,  DIMA VINCENZO

    IPC: G11C16/28

    Abstract: The present invention relates a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor comprising a mirror transistor, a first transistor and a second transistor, said mirror transistor and said first transistor having in common the gate electrodes in a circuit node, said second transistor being connected in a transdiode configuration and placed between the gate electrode and the drain electrode of said first transistor, and a current source being connected to the gate electrode of said first transistor and to the drain electrode of said second transistor, characterized by comprising a third transistor which is configured to receive a switching signal at its gate electrode and is connected between the drain and the gate electrode of said first transistor.

    10.
    发明专利
    未知

    公开(公告)号：IT1314122B1

    公开(公告)日：2002-12-04

    申请号：ITMI992576

    申请日：1999-12-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DIMA VINCENZO ,  BEDARIDA LORENZO ,  GERACI ANTONINO ,  BARTOLI SIMONE

    IPC: G05F3/24

    Abstract: An output buffer device having first and second supply voltage references, the first voltage reference being lower in value than the second voltage reference. The output buffer device includes first and second complementary MOS transistors, which transistors are connected in series together between one of the supply voltage references and a further voltage reference, have gate terminals connected together and to an input terminal of this buffer device, and have drain terminals connected together and to an output terminal of the buffer device. Advantageously, the first transistor is connected to the first supply voltage reference. Furthermore, the output buffer device comprises at least one additional drive MOS transistor of the same type as the first MOS transistor and placed between the second supply voltage reference and the output terminal of the buffer device.

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