公开(公告)号：JPH06224689A

公开(公告)日：1994-08-12

申请号：JP18823293

申请日：1993-07-29

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO

IPC: H03F1/34 ,  H03H7/06 ,  H03H11/04 ,  H03H11/12 ,  H04M1/00

Abstract: PURPOSE: To provide an inexpensive high-accuracy RC filter having structural and operational features suitable for integrated circuits requiring very large time constants. CONSTITUTION: An RC filter 1 is provided with a resistor R connected between the input Vin and output Vout of the filter and an amplifier 5 which is connected behind the resistor R and the output of which is fed back to its input through a capacitor. By using such a simple device, a filter having a large time constant while using small-sized components occupying small spaces in an integrated circuit can be manufactured by utilizing the already known mirror effect.

公开(公告)号：JPH06216733A

公开(公告)日：1994-08-05

申请号：JP23338493

申请日：1993-09-20

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO ,  CONFALONIERI PIERANGELO

IPC: H03K17/06 ,  H03K17/687

Abstract: PURPOSE: To unnecessitate activation time until reaching an ordinary state by setting the clock cycle of output terminal at the maximum power voltage value from the beginning by composing a driver circuit for electronic switch of an input pin for impressing a clock signal and a voltage duplexer connected between this pin and a switch. CONSTITUTION: In this driver circuit 1 for an electronic switch 2, the switch 2 is operated corresponding to the clock signal at a prescribed frequency. The switch 2 is composed of an N channel MOS transistor M3, its gate terminal is connected to an output terminal 0 of circuit 1 and its drain terminal and source terminal are functioned as switch terminals. The circuit 1 is provided with a pair of FET M1 and M2, and their drain terminals D1 and D2 are also connected to the terminal 0 together. When operating the circuit 1 in such configuration, a phase F at an input pin B is made high, the phase F at a pin A is made low, in such a state, the gate/source voltage drop of transistor M1 is made equal with a power supply voltage Vdd, the M2 is not conducted and a capacitor C is turned into charged state.

公开(公告)号：JPH05252320A

公开(公告)日：1993-09-28

申请号：JP27013592

申请日：1992-10-08

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO

IPC: H04M1/00 ,  H04M19/08

Abstract: PURPOSE: To provide a circuit array which constitutes a speech circuit having extremely small voltage loss of a telephone line. CONSTITUTION: This array consists of an operational amplifier A, two resistors R1 and R2 connected between a telephone line and the input of the amplifier, 1st and 2nd FETs M1 and M2 connected to the output of the amplifier, 1st and 2nd bipolar transistors P1 and P2 which are controlled by the amplifier through the FETs, two current generators CC1 and CC2 , and a capacitor C connected to the collector terminal of the 2nd bipolar transistor, and the voltage of the telephone line is obtained as a stabilized voltage VS across the capacitor through the circuit array. Currents I1 and I2 from the generators and other electric physical quantities as circuit constants are so set that the 1st and 2nd bipolar transistors are turned off and on respectively when the voltage of the telephone line is smaller than a specific minimum value and on and off when not.

公开(公告)号：US6411166B2

公开(公告)日：2002-06-25

申请号：US86491601

申请日：2001-05-23

Applicant: ST MICROELECTRONICS SRL

Inventor： BASCHIROTTO ANDREA ,  CUSINATO PAOLO ,  MONTAGNA GIAMPIERO ,  CASTELLO RINALDO

IPC: H03F3/00 ,  H03F3/45

CPC classification number: H03F3/4565 ,  H03F3/005 ,  H03F3/45183

Abstract: A switched operational amplifier with fully differential topology, alternately switchable on and off, and a control circuit. The operational amplifier has a first differential output (4a) and a second differential output, and a control terminal. The control circuit includes a capacitive detecting network including a first capacitor and a second capacitor connected between the first and second differential outputs and a common-mode node, and a third capacitor connected between the common-mode node and ground in a first operative condition, and between the common-mode node and the supply voltage in a second operative condition. A control transistor is connected between the common-mode node and the control terminal of the operational amplifier and supplies a control current correlated to the voltage on the common-mode node. A switchable voltage source, connected to the common-mode node, supplies a desired voltage in a first operative condition, when the operational amplifier is off.

公开(公告)号：DE69621615D1

公开(公告)日：2002-07-11

申请号：DE69621615

申请日：1996-10-11

Applicant: ST MICROELECTRONICS SRL

Inventor： BASCHIROTTO ANDREA ,  NAGARI ANGELO ,  CASTELLO RINALDO

IPC: H03F1/08 ,  H03F3/72 ,  H03H1/00

Abstract: In a switched operational amplifier including a differential input stage and at least a second output stage the compensation capacitor (CC) commonly required to couple the output node of the second stage with the respective output node of the input differential stage of the amplifier is associated with switching means (M5P, M5N) controlled by the same control phase (Ph1) that enables/disables the amplifier for interrupting the connection between the compensation capacitor (CC) and the output node of the differential input stage during a phase in which the amplifier is disabled for reducing the switch-on time. Notably the differential input stage of the operational amplifier remains always active and only the second output stage is switched on and off.

公开(公告)号：DE69228420T2

公开(公告)日：1999-06-24

申请号：DE69228420

申请日：1992-09-16

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO

IPC: H04M19/08

Abstract: A certain amount of DC supply current derivable from a subscriber's line (VL, GROUND) is used for powering at respective regulated voltages a plurality of functional circuits (A,B...) of an equipment connectable to the line. A sensible energy saving can be achieved by splitting the valuable current among the functional circuits, on account of their priority rank, by using at least a differential pair of current delivering transistors (P2,P3). A special circuit monitors the actual current of absorption of the functional circuit of highest rank (A) and produces a control signal that is used for modifying the drive conditions of the current delivering transistors. The current waste caused by sinking a design maximum current through a dissipative shunt voltage regulator of each functional circuit as done in the prior art circuits, is prevented and all the current exceeding the actual absorption needs of the highest rank functional circuit may be distributed to the other functional circuits without waste. This same principle may be advantageously applied also to functional circuits of lesser and lesser rank of priority for maximizing the saving.

公开(公告)号：DE69228807D1

公开(公告)日：1999-05-06

申请号：DE69228807

申请日：1992-07-22

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO ,  ERRATICO PIETRO

IPC: H04B1/58 ,  H04M1/58 ,  H04M1/76 ,  H04M1/00

Abstract: A circuit (1) for synthesizing an impedance associated with a telephone subscriber's circuit (2) connected to a two-wire telephone line (3) is a positive feedback configuration comprising: a single precision resistance (R) connected serially to the line (3); at least one low-pass filter; and an amplifier (7) between the filter (8) and the resistance (R). This circuit (1) allows both the termination impedance and the balance impedance to be synthesized through a single external precision component.

公开(公告)号：DE69529908T2

公开(公告)日：2003-12-04

申请号：DE69529908

申请日：1995-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO ,  CLERICI GIANCARLO ,  BIETTI IVAN

IPC: H03F1/08 ,  H03F1/14 ,  H03F1/34 ,  H03F1/00

Abstract: An operational amplifier frequency self-compensated with respect to closed-loop gain comprises a transconductance input stage (2) and an amplifier output stage (3) connected serially together to receive an input signal (Sin) on at least one input terminal (IN) of the amplifier and generate an amplified signal (Sout) on an output terminal (OUT) of the amplifier. Provided between the input (2) and output (3) stages is an intermediate node (S) which is connected to a compensation block (11) to receive a frequency-variable compensation signal (Sc) therefrom. According to the invention, the compensation block (11) is coupled with its input to the input terminal (IN) of the amplifier. The compensation block (11) is connected to receive at least the feedback signal (Sf). Preferably, the compensation signal (Sc) is variable as a function of a gain value (Gcl) which is determined by the feedback circuit, and said variation of the compensation signal occurs in a relationship of inverse proportionality to the gain value. This invention is useful in discrete circuits whose operational amplifier forms a device by itself, as well as in fully integrated circuits.

公开(公告)号：DE69529401D1

公开(公告)日：2003-02-20

申请号：DE69529401

申请日：1995-05-22

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMASINI LUCIANO ,  CASTELLO RINALDO ,  BIETTI IVAN ,  CLERICI GIANCARLO

IPC: H03F3/45 ,  H03H1/00

公开(公告)号：DE69428785T2

公开(公告)日：2002-07-04

申请号：DE69428785

申请日：1994-06-30

Applicant: ST MICROELECTRONICS SRL

Inventor： REZZI FRANCESCO ,  BASCHIROTTO ANDREA ,  CASTELLO RINALDO

IPC: H03F3/34 ,  H03F3/45 ,  H03H11/04