公开(公告)号：JPH0817848A

公开(公告)日：1996-01-19

申请号：JP15598295

申请日：1995-06-22

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/739

Abstract: PURPOSE: To ignore the base series resistance of a parasitic perpendicular bipolar transistor by adjusting an ion implantation energy so that the peak of the dopant concentration of a heavily doped part of a body region is located on the lower side of a source region than the surface of a semiconductor layer. CONSTITUTION: With an insulation gate layer 10 on the surface of a semiconductor layer 3 as a mask, a first impurity is ion-implanted with an energy in a specific thickness from the surface of the semiconductor layer 3 and is thermally diffused, thus forming a body region 2 consisting of a first greatly doped part 5 that is nearly aligned to both edges of the insulation layer 10 and a horizontal diffusion part 6 at the lower side of the insulation layer 10. The second impurity is ion-implanted selectively into the body region 2 in a pair, thus forming an annular source 7 that is aligned to both edges of the insulation layer 10, thus forming the greatly doped part 5 of the first impurity so that it is located at the lower side of the annular source region 7 and ignoring the base series resistance of a parasitic perpendicular bipolar transistor.

公开(公告)号：JPH03173169A

公开(公告)日：1991-07-26

申请号：JP30894190

申请日：1990-11-16

Applicant: ST MICROELECTRONICS SRL

Inventor： FERLA GIUSEPPE ,  PALARA SERGIO

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H01L27/082 ,  H01L29/732

Abstract: PURPOSE: To stabilize the operational characteristics by entirely covering the projecting end of an insulating pocket with a first grounded metallization part. CONSTITUTION: In order to overcome voltage rise at an insulation pocket P caused by the presence of a parasitic transistor, projecting end of the insulating pocket is covered entirely with a metallization part 21, e.g. a metal polysilicide, preferably a platinum layer. It has a resistance of about 1Ω/square which is about 100 times as low as that of the insulation pocket P. Some region of the insulation pocket Preaches a grounded metal track of aluminum and comes into contact therewith. Since the leakage current of parasitic transistors T3, T4 is passed through a low resistance path and grounded, it causes no voltage rise at the insulation pocket P.

公开(公告)号：DE602005017457D1

公开(公告)日：2009-12-17

申请号：DE602005017457

申请日：2005-11-18

Applicant: ST MICROELECTRONICS SRL

Inventor： FERRUCCIO FRISINA ,  FERLA GIUSEPPE ,  MAGRI ANGELO ,  GRIMALDI ANTONIO GIUSEPPE ,  BAZZANO GAETANO

IPC: H01L29/78 ,  H01L29/49

公开(公告)号：DE69518653D1

公开(公告)日：2000-10-05

申请号：DE69518653

申请日：1995-12-28

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： GRIMALDI ANTONIO ,  SCHILLACI ANTONINO ,  FRISINA FERRUCCIO ,  FERLA GIUSEPPE

IPC: H01L21/336 ,  H01L23/482 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/739

公开(公告)号：DE69229927D1

公开(公告)日：1999-10-14

申请号：DE69229927

申请日：1992-03-17

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FRISINA FERRUCCIO FRISINA FERR ,  FERLA GIUSEPPE

IPC: H01L21/22 ,  H01L21/322 ,  H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/07 ,  H01L27/082 ,  H01L29/732 ,  H01L29/861

Abstract: The structure consists of a single chip (1) of semiconductor material, which comprises an area (32) having a high lifetime of the minority carriers, which constitutes a bipolar power device with high current density, and at least one area (20, 21; 20', 21') with a reduced lifetime of the minority carriers, which constitutes a fast diode.

公开(公告)号：DE69418037D1

公开(公告)日：1999-05-27

申请号：DE69418037

申请日：1994-08-02

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/768 ,  H01L23/12 ,  H01L23/482 ,  H01L21/60 ,  H01L23/495 ,  H01L23/522 ,  H01L29/417 ,  H01L29/78 ,  H01L29/72

Abstract: In a MOS-technology power device chip and package assembly, the MOS-technology power device chip (1) comprises a semiconductor material layer (4,5) in which a plurality of elementary functional units (6) is integrated, each elementary functional unit (6) contributing for a respective fraction to an overall current and comprising a first doped region (7) of a first conductivity type formed in said semiconductor layer (4,5), and a second doped region (10) of a second conductivity type formed inside said first doped region (7); the package (2) comprises a plurality of pins (P1-P10) for the external electrical and mechanical connection; said plurality of elementary functional units (6) is composed of sub-pluralities of elementary functional units (6), the second doped regions (10) of all the elementary functional units (6) of each sub-plurality being contacted by a same respective metal plate (100) electrically insulated from the metal plates (100) contacting the second doped regions (10) of all the elementary functional units (6) of the other sub-pluralities; each of said metal plate (100) is connected, through a respective bonding wire (W1-W5), to a respective pin (P1-P5) of the package (2).

公开(公告)号：DE602005025845D1

公开(公告)日：2011-02-24

申请号：DE602005025845

申请日：2005-11-18

Applicant: ST MICROELECTRONICS SRL

Inventor： ARENA GIUSEPPE ,  FERLA GIUSEPPE ,  CAMALLERI MARCO

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423

公开(公告)号：DE69834499T2

公开(公告)日：2007-04-19

申请号：DE69834499

申请日：1998-12-22

Applicant: ST MICROELECTRONICS SRL

Inventor： PALMISANO GIUSEPPE ,  FERLA GIUSEPPE ,  GIRLANDO GIOVANNI

IPC: H03F1/56 ,  H03F1/22

Abstract: The amplifier stage (50) comprises a first (2) and a second (3) transistor, connected in series to each other between a first (4) and a second (5) reference potential line. The first transistor (2) has a control terminal (10), connected to an input (11) of the amplifier stage (50) through a first inductor (12), a first terminal (15), connected to the second reference potential line (5) through a second inductor (16), and a third terminal (17) connected to a first terminal of the second transistor (3). The second transistor has a second terminal (21) forming an output of the amplifier stage (50), and connected to the first reference potential line (4) through a load resistor (22). To improve the noise figure, a matching capacitor (51) is connected between the control terminal (10) and the first terminal (15) of the first transistor (2).

公开(公告)号：DE69434937D1

公开(公告)日：2007-04-19

申请号：DE69434937

申请日：1994-06-23

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

Abstract: A zero thermal budget process for the manufacturing of a MOS-technology vertical power device (such as a MOSFET or a IGBT) comprises the steps of: forming a conductive Insulated gate layer (8) on a surface of a lightly doped semiconductor material layer (3) of a first conductivity type; selectively removing the insulated gate layer (8) from selected portions of the semiconductor material layer (3) surface; selectively implanting a first dopant of a second conductivity type into said selected portions of the semiconductor material layer (3), the insulated gate layer (8) acting as a mask, in a dose and with an implantation energy suitable to obtain, directly after the implantation, heavily doped regions (5) substantially aligned with the edges of the insulated gate layer (8); selectively implanting a second dopant of the second conductivity type along directions tilted of prescribed angles ( alpha 1, alpha 2) with respect to a direction orthogonal to the semiconductor material layer (3) surface, the insulated gate layer (8) acting as a mask, in a dose and with an implantation energy suitable to obtain, directly after the implantation, lightly doped channel regions (6) extending under the insulated gate layer (8); selectively implanting a heavy dose of a third dopant of a first conductivity type into the heavily doped regions (5), to form source regions (7) substantially aligned with the edges of the insulated gate layer (8).

公开(公告)号：DE69834499D1

公开(公告)日：2006-06-14

申请号：DE69834499

申请日：1998-12-22

Applicant: ST MICROELECTRONICS SRL

Inventor： PALMISANO GIUSEPPE ,  FERLA GIUSEPPE ,  GIRLANDO GIOVANNI

IPC: H03F1/56 ,  H03F1/22

Abstract: The amplifier stage (50) comprises a first (2) and a second (3) transistor, connected in series to each other between a first (4) and a second (5) reference potential line. The first transistor (2) has a control terminal (10), connected to an input (11) of the amplifier stage (50) through a first inductor (12), a first terminal (15), connected to the second reference potential line (5) through a second inductor (16), and a third terminal (17) connected to a first terminal of the second transistor (3). The second transistor has a second terminal (21) forming an output of the amplifier stage (50), and connected to the first reference potential line (4) through a load resistor (22). To improve the noise figure, a matching capacitor (51) is connected between the control terminal (10) and the first terminal (15) of the first transistor (2).