中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

27 records (took 0.024 seconds)

    15.
    发明专利
    未知

    公开(公告)号：DE69516402D1

    公开(公告)日：2000-05-25

    申请号：DE69516402

    申请日：1995-07-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CALLIGARO CRISTIANO ,  DANIELE VINCENZO ,  GASTALDI ROBERTO ,  MANSTRETTA ALESSANDRO ,  TELECCO NICOLA ,  TORELLI GUIDO

    IPC: G11C11/56

    Abstract: A method for sensing multiple-levels non-volatile memory cells which can take one programming level among a plurality of m=2 (n > = 2) different programming levels, provides for biasing a memory cell (MC) to be sensed in a predetermined condition, so that the memory cell (MC) sinks a cell current (IC) with a value belonging to a discrete set of m distinct cell current values (IC0-IC15), each cell current value (IC0-IC15) corresponding to one of said programming levels. The sensing method also provides for: simultaneously comparing the cell current (IC) with a prescribed number of reference currents (IR1,IR2,IR3) having values comprised between a minimum value and a maximum value of said discrete set of m cell current values (IC0-IC15) and dividing said discrete set of m cell current values (IC0-IC15) in a plurality of sub-sets of cell current values, for determining the sub-set of cell current values to which the cell current (IC) belongs; repeating step a) for the sub-set of cell current values to which the cell current (IC) belongs, until the sub-set of cell current values to which the cell current (IC) belongs comprises only one cell current value, which is the value of the current (IC) of the memory cell (MC) to be sensed.

    16.
    发明专利
    未知

    公开(公告)号：DE69514783D1

    公开(公告)日：2000-03-02

    申请号：DE69514783

    申请日：1995-03-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CALLIGARO CRISTIANO ,  DANIELE VINCENZO ,  GASTALDI ROBERTO ,  MANSTRETTA ALESSANDRO ,  TELECCO NICOLA ,  TORELLI GUIDO

    IPC: G11C16/04 ,  G11C11/56 ,  G11C16/02 ,  G11C17/00

    Abstract: A sensing circuit for serial dichotomic sensing of multiple-levels memory cells (MC) which can take one programming level among a plurality of m=2 (n >= 2) different programming levels, comprises biasing means for biasing a memory cell (MC) to be sensed in a predetermined condition, so that the memory cell (MC) sinks a cell current (IC) with a value belonging to a plurality of m distinct cell current values (IC0-IC3), each cell current value (IC0-IC3) corresponding to one of the programming levels, a current comparator (1) for comparing the cell current (IC) with a reference current (IR) generated by a variable reference current generator (G), and a successive approximation register (2) supplied with an output signal (CMP) of the current comparator (1) and controlling the variable reference current generator (G). The variable reference current generator comprises an offset current generator (Ioff) permanently coupled to the current comparator (1), and m-2 distinct current generators (IR0,IR1), independently activatable by the successive approximation register (2), each one generating a current (IC1,IC2) equal to a respective one of the plurality of cell current values (IC0-IC3).

    17.
    发明专利
    未知

    公开(公告)号：DE69726136D1

    公开(公告)日：2003-12-18

    申请号：DE69726136

    申请日：1997-08-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ROLANDI PAOLO ,  GASTALDI ROBERTO ,  CALLIGARO CRISTIANO

    IPC: G11C11/56 ,  G11C16/08 ,  G11C16/30 ,  G11C11/00 ,  G11C16/06

    Abstract: The present invention relates to a circuit for generating a regulated voltage (RV), in particular for gate terminals of non-volatile memory cells of the floating gate type, which comprises a generator circuit (OSC,CHP) adapted to generate an unregulated voltage (VCHP) on its output, a comparator circuit coupled to the output of the generator circuit (OSC,CHP), including a reference element consisting of a non-volatile memory cell (REFC) of the floating gate type and adapted to output an electric error signal (ID) tied to the difference between the unregulated voltage (VCHP) and the threshold voltage of the cell (REFC), and a regulator circuit (CSEL,CBIAS,IVC,DRV,TR) coupled to the output of the comparator circuit and operative to regulate the unregulated voltage (VCHP) based on the value of the electric error signal (ID). Through the present circuit, the regulated voltage (RV) is made programmable and tied to the parameters of the memory cell (REFC).

    20.
    发明专利
    未知

    公开(公告)号：DE69526336D1

    公开(公告)日：2002-05-16

    申请号：DE69526336

    申请日：1995-04-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CALLIGARO CRISTIANO ,  GASTALDI ROBERTO ,  TELECCO NICOLA ,  TORELLI GUIDO

    IPC: G11C11/419 ,  G11C7/06 ,  G11C11/00

    Abstract: A reading device for devices with memory cells with two branches each comprising, connected in cascade, an electronic switch (T3, T4), an active element (T1, T2) reactively connected to the active element of the other branch, between them to form a voltage amplifier. Each active element is controlled by means of a high impedance circuit element (DL, DR). A microswitch (TE) which connects the two branches together is inserted between the two active elements (1, 2).

Patent Agency Ranking