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公开(公告)号：JPH0883494A
公开(公告)日：1996-03-26
申请号：JP5377795
申请日：1995-02-20
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA , MACCARRONE MARCO , OLIVO MARCO
Abstract: PURPOSE: To obtain a timer which can be constituted by a slow element excellent in noise characteristics. CONSTITUTION: This embodiment is a nonvolatile memory 100 comprising a data amplifier 106 and an output element 108 connecting with each other via a connection line 107. A noise suppression circuit 1 comprises networks 8, 18 for generating a noise suppression signal N which is synchronized completely with a signal L for controlling a data loading from the amplifier 106 to the output device 108. A very short lasting time period same as a switch time period of the output device 108 is given, and when the output device 108 is switched, the amplifier 106 is frozen, and data stored in the amplifier or an internal circuit of the memory 100 cannot be changed. An address amplifier 102 on address buses 101, 103 is blockaded according to the same signal.
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公开(公告)号：JPH07262792A
公开(公告)日：1995-10-13
申请号：JP30221994
申请日：1994-12-06
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA
Abstract: PURPOSE: To reduce a chip area by unnecessitating any protection memory cell by forming a combined circuit for generating a signal for inhibiting the selection of any memory cell. CONSTITUTION: A non-volatile register 1 is formed from memory cells MC0-MCn and a redundant word line selection circuit 2. The cells MC0-MCn have output signals CMP0-CMPn to be activated when row address signals are coincident with memories. The selection circuit 2 inputs all the signals CM0-CMPn and generates signals RS0-RSi for selecting any one redundant line word and preventing the defective word line of which the address is coincident with the address stored in the register from being selected. Besides, a combined circuit 3 generates a signal DIS for inhibiting the selection circuit 2 from generating the signals RS0-RSi. The protection memory cell is unnecessitated by a redundant circuit formed from the selection circuit 2 and the combined circuit 3.
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公开(公告)号：JP2675277B2
公开(公告)日：1997-11-12
申请号：JP8842895
申请日：1995-04-13
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA , MACCARRONE MARCO
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公开(公告)号：JP2591923B2
公开(公告)日：1997-03-19
申请号：JP31188894
申请日：1994-12-15
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA MARIA , OLIVO MARCO
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公开(公告)号：JPH08147994A
公开(公告)日：1996-06-07
申请号：JP2943995
申请日：1995-02-17
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA MARIA , MACCARRONE MARCO
Abstract: PURPOSE: To effectively program a redundancy register in a row redundancy integrated circuit. CONSTITUTION: Row address signals R0 to R9 are supplied to nonvolatile memory registers RR1 to RR4, select signals C0 to C3 belonging to one set of column address signals are supplied, the addresses of first fault row pair are supplied to the row address signals, one of the select signal for selecting the registers RR1 to RR is set operable, and the signal of first logic level is supplied to other signal C4. The first subset of the two subsets of memory cells is programmed with the selected register to make it possible to program the address of the first fault rows of the a pair of adjacent fault row to the first subset of the cell, the address of the pair of second fault row of te adjacent fault column is supplied to at least subset of the row address signal, the second reverse logic level signal is supplied to the other signal of one set of the column address signal, and the programming of the address of the air of second fault row of the adjacent fault row to the second subset of the cell can be performed.
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Patent Agency Ranking
公开(公告)号：JPH0845282A
公开(公告)日：1996-02-16
申请号：JP8842895
申请日：1995-04-13
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA , MACCARRONE MARCO
Abstract: PURPOSE: To realize high rate reading by providing a reference cell with additional current branches including a parallel transistor(TR) thereby setting the ratio between cell current and reference current higher at the time of equivalent step than at the time of evaluation step. CONSTITUTION: Bit line 5 and reference line 11 of a read circuit 1 are precharged with precharge circuits 4, 10 before an equivalent step and following evaluation step are carried out and the content stored in a cell 6 is read out through a sense amplifier 17. This circuit 1 is additionally provided with a current branch 31 comprising additional current TR 43, TR 44 having one end grounded through a line 11 and the other end grounded through a switching transistor 44 and the ratio between cell current and reference current on the lines 5, 11 is set higher at the time of equivalent step than at the time of evaluation step. Consequently, the current of a load means 8 is controlled quickly at the time of evaluation step and high rate reading is realized.
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公开(公告)号：DE69636161D1
公开(公告)日：2006-06-29
申请号：DE69636161
申请日：1996-07-30
Applicant: ST MICROELECTRONICS SRL
Inventor： GHILARDELLI ANDREA , GHEZZI STEFANO , GOLLA CARLA MARIA
IPC: H01L29/94
Abstract: A MOS capacitor comprises a semiconductor substrate (2), a first well region (1;8) of a first conductivity type formed in the substrate, at least one doped region (4;11) formed in the first well region, and an insulated gate layer (5,6) insulatively disposed over a surface of the first well region. The at least one doped region and the insulated gate layer respectively form a first and a second electrode of the capacitor. The first well region is electrically connected to the at least one doped region to be at a same electrical potential of the first terminal of the capacitor.
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公开(公告)号：DE69324694D1
公开(公告)日：1999-06-02
申请号：DE69324694
申请日：1993-12-15
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA MARIA , OLIVO MARCO
Abstract: A plurality of identical circuit blocks (PG0-PG15) is supplied with address signals (A0-A3,A0N-A3N) and each one generating a respective selection signal (P0-P15) which is activated by a particular logic configuration of said address signals (A0-A3,A0N-A3N) for the selection of a particular row (WL0-WL15) of the matrix; each one of said circuit blocks (PG0-PG15) also generates a carry-out signal (C00-C015) which is supplied to a carry-in input (CI0-CI15) of a following circuit block (PG0-PG15) and is activated when the respective selection signal (P0-P15) is activated; a first circuit block (PG0) of said plurality of circuit blocks (PG0-PG15) has the respective carry-in input (C10) connected to a reference voltage (GND); each of said circuit blocks (PG0-PG15) is also supplied with a control signal (E), which is activated by a control circuitry (6) of the memory device when, during a preprogramming operation preceding an electrical erasure of the memory device, a defective row (WL0-WL15) is addressed, to enable the activation of the respective selection signal (P0-P15) if the carry-out (C00-C014) signal supplying the respective carry-in input (CI1-CI15) is activated, so that two adjacent rows (WL0-WL15) can be simultaneously selected.
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公开(公告)号：DE69615149D1
公开(公告)日：2001-10-18
申请号：DE69615149
申请日：1996-03-06
Applicant: ST MICROELECTRONICS SRL
Inventor： GOLLA CARLA MARIA , ZAMMATTIO MATTEO , ZANARDI STEFANO
IPC: G11C8/18 , H03K5/1534 , H03K3/011 , H03K3/355 , G11C8/00
Abstract: An address transition detection circuit (30) having a number of cells (1) supplied with respective address signals and output connected in a wired NOR configuration to generate a pulse signal (WN) on detecting transitions of their respective address signals. The pulse signal is supplied to a source stage for generating an address transition signal (ATDO) having a first and second switching edge on receiving the pulse signal. The source stage has a monostable stage (80) for generating an end-of-transition signal (ATDY) with a predetermined delay following reception of the pulse signal; and an output stage (35, 70) connected to the cells (1) and to the monostable stage (80), which generates the first switching edge of the address transition signal (ATDO) on receiving the pulse signal (WN), and the second switching edge on receiving the end-of-transition signal. The monostable stage (80) presents a compensating structure (40, 42, 44) for maintaining the delay in the switching of the end-of-transition signal (ATDY) stable alongside variations in temperature and supply voltage.
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公开(公告)号：DE69425367T2
公开(公告)日：2001-02-15
申请号：DE69425367
申请日：1994-04-19
Applicant: ST MICROELECTRONICS SRL
Inventor： PASCUCCI LUIGI , GOLLA CARLA MARIA , MACCARRONE MARCO
Abstract: A read circuit (1) comprising at least one array branch (2) connected to at least one bit line (5), and a reference branch (3) connected to a reference line (11). The array and reference branches each comprise a precharge circuit (4, 10) and load (8, 13, 15) interposed between the supply (7) and the bit line (5) and reference line (11) respectively. The reference load (13, 15) is so formed as to generate a reference current which, during evaluation, is twice the current supplied to the bit line (5). The reference line (11) is connected to an extra-current transistor (43) which is only turned on during equalization so that, during equalization, the selected bit line (5) is supplied with a high current approximating that supplied to the reference line (11). As such, if the cell to be read (6) is written, the output voltage of the array branch (2) is brought rapidly to its natural high value; whereas, if the cell to be read is erased, the output voltage may return to its low value when the extra-current transistor is turned off, thus permitting reading in advance.
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