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    METHOD FOR PROGRAMMING OF REDUNDANT REGISTER INTO ROW REDUNDANT INTEGRATED CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICEAND ROW REDUNDANT INTEGRATED CIRCUIT
    12.
    发明专利
    METHOD FOR PROGRAMMING OF REDUNDANT REGISTER INTO ROW REDUNDANT INTEGRATED CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICEAND ROW REDUNDANT INTEGRATED CIRCUIT 失效

    公开(公告)号：JPH08147994A

    公开(公告)日：1996-06-07

    申请号：JP2943995

    申请日：1995-02-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GOLLA CARLA MARIA ,  MACCARRONE MARCO

    IPC: G11C29/00 ,  G11C29/04

    Abstract: PURPOSE: To effectively program a redundancy register in a row redundancy integrated circuit. CONSTITUTION: Row address signals R0 to R9 are supplied to nonvolatile memory registers RR1 to RR4, select signals C0 to C3 belonging to one set of column address signals are supplied, the addresses of first fault row pair are supplied to the row address signals, one of the select signal for selecting the registers RR1 to RR is set operable, and the signal of first logic level is supplied to other signal C4. The first subset of the two subsets of memory cells is programmed with the selected register to make it possible to program the address of the first fault rows of the a pair of adjacent fault row to the first subset of the cell, the address of the pair of second fault row of te adjacent fault column is supplied to at least subset of the row address signal, the second reverse logic level signal is supplied to the other signal of one set of the column address signal, and the programming of the address of the air of second fault row of the adjacent fault row to the second subset of the cell can be performed.

    MEMORY-ARRAY-CELL READ CIRCUIT
    13.
    发明专利
    MEMORY-ARRAY-CELL READ CIRCUIT 失效

    公开(公告)号：JPH0845282A

    公开(公告)日：1996-02-16

    申请号：JP8842895

    申请日：1995-04-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  GOLLA CARLA MARIA ,  MACCARRONE MARCO

    IPC: G11C17/00 ,  G11C16/06 ,  G11C16/24 ,  G11C16/28

    Abstract: PURPOSE: To realize high rate reading by providing a reference cell with additional current branches including a parallel transistor(TR) thereby setting the ratio between cell current and reference current higher at the time of equivalent step than at the time of evaluation step. CONSTITUTION: Bit line 5 and reference line 11 of a read circuit 1 are precharged with precharge circuits 4, 10 before an equivalent step and following evaluation step are carried out and the content stored in a cell 6 is read out through a sense amplifier 17. This circuit 1 is additionally provided with a current branch 31 comprising additional current TR 43, TR 44 having one end grounded through a line 11 and the other end grounded through a switching transistor 44 and the ratio between cell current and reference current on the lines 5, 11 is set higher at the time of equivalent step than at the time of evaluation step. Consequently, the current of a load means 8 is controlled quickly at the time of evaluation step and high rate reading is realized.

    METHOD AND CIRCUIT FOR SUPPRESSION OF DATA LOADING NOISE IN NONVOLATILE MEMORY
    15.
    发明专利
    METHOD AND CIRCUIT FOR SUPPRESSION OF DATA LOADING NOISE IN NONVOLATILE MEMORY 失效

    公开(公告)号：JPH0883494A

    公开(公告)日：1996-03-26

    申请号：JP5377795

    申请日：1995-02-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  GOLLA CARLA MARIA ,  MACCARRONE MARCO ,  OLIVO MARCO

    IPC: G11C11/413 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/32 ,  G11C17/00

    Abstract: PURPOSE: To obtain a timer which can be constituted by a slow element excellent in noise characteristics. CONSTITUTION: This embodiment is a nonvolatile memory 100 comprising a data amplifier 106 and an output element 108 connecting with each other via a connection line 107. A noise suppression circuit 1 comprises networks 8, 18 for generating a noise suppression signal N which is synchronized completely with a signal L for controlling a data loading from the amplifier 106 to the output device 108. A very short lasting time period same as a switch time period of the output device 108 is given, and when the output device 108 is switched, the amplifier 106 is frozen, and data stored in the amplifier or an internal circuit of the memory 100 cannot be changed. An address amplifier 102 on address buses 101, 103 is blockaded according to the same signal.

    CHARGE PUMP CIRCUIT
    16.
    发明专利
    CHARGE PUMP CIRCUIT 失效

    公开(公告)号：JPH0847246A

    公开(公告)日：1996-02-16

    申请号：JP1306395

    申请日：1995-01-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  MACCARRONE MARCO ,  PADOAN SILVIA

    IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  H02M3/07

    Abstract: PURPOSE: To supply large power in the case that an input/output voltage ratio is low or a power supply voltage is low by mutually connecting in parallel pull-up stages between a reference potential line and an output line. CONSTITUTION: This charge pump circuit 1 is provided with numerous stages 21 -2n connected in parallel to each other between the reference potential line 3 and the output line 4, the respective stages 21 -2n are provided with bootstrap capacitors 51 -5n , the one side is connected to nodes 71 -7n and the other terminals are connected to nodes 61 -6n . Then, when inverters 121 -12n are switched, the odd-numbered stages 21 , 23 ,... are switched to a charge transfer mode, the even- numbered stages are switched to a charging mode. When a switching edge reaches a stage 2n-1 which is one next to the last, an AND circuit 15 and a NOR circuit 16 are switched, shifting along the inverters 121 -12n is performed, the odd-numbered stages 21 , 23 ,... are charged, and the even-numbered stages 22 , 24 ,... transfer the stored charges. As a result, even in the case that an input voltage ratio is low, voltage is efficiently boosted and a large power is supplied.

    METHOD AND CIRCUIT FOR LOADING TIMING OF OUTPUT DATA OF NONVOLATILE MEMORY
    17.
    发明专利
    METHOD AND CIRCUIT FOR LOADING TIMING OF OUTPUT DATA OF NONVOLATILE MEMORY 失效

    公开(公告)号：JPH0845289A

    公开(公告)日：1996-02-16

    申请号：JP5377695

    申请日：1995-02-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  MACCARRONE MARCO ,  OLIVO MARCO

    IPC: G11C17/00 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/32

    Abstract: PURPOSE: To set a timing accurately while suppressing noise by loading a simulate signal to an output simulation circuit through a switch subjected to required control and resetting a simulate generation circuit in response to the variation of simulate signal. CONSTITUTION: Upon provision of a sync signal SYNC, a simulate signal SP is generated from the simulate signal generator 34 of delay FF and a load block signal SS makes a transition to L through a switch 35 opened by a load enable signal L before being loaded to an unblocked output simulation circuit 21. When the signal SP is inverted to 'L', output is inverted to H through a NAND gate 30 and an inverter 32 and the generator 34 is reset instantaneously through a monostable multivibrator 33. On the other hand, a signal SS is inverted to H and loading to the circuit 21 is blocked. According to the circuitry, loading of signal and blocking of loading are controlled accurately and the effect of noise due to housing is suppressed.

    CIRCUIT DEVICE FOR MEASURING DISTRIBUTION OF THRESHOLD VOLTAGE IN NONVOLATILE MEMORY-CELL
    18.
    发明专利
    CIRCUIT DEVICE FOR MEASURING DISTRIBUTION OF THRESHOLD VOLTAGE IN NONVOLATILE MEMORY-CELL 失效

    公开(公告)号：JPH07272500A

    公开(公告)日：1995-10-20

    申请号：JP7186195

    申请日：1995-03-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PADOAN SILVIA ,  MACCARRONE MARCO ,  OLIVO MARCO

    IPC: G11C17/00 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56 ,  G11C16/06

    Abstract: PURPOSE: To improve and facilitate the measurement of the distribution of threshold voltage in a non-volatile memory-cell further. CONSTITUTION: A circuit device 1 for measuring the distribution of threshold voltage has a differential amplifier 3 connected to a circuit leg containing a memory-cell 2 and a reference circuit leg 4 and a circuit means unbalancing the values of currents flowing through each circuit leg. The circuit means comprises a variable current generator related to the reference circuit leg 4, the variable current generator is connected between a supply-voltage Vdd reference point and a ground-voltage GND reference point, and a current I2 as the function of supply voltage Vdd is generated in the reference circuit leg 4.

    INTEGRATED CIRCUIT FOR CHECKING OF USE RATE OF REDUNDANCY MEMORY ELEMENT
    19.
    发明专利
    INTEGRATED CIRCUIT FOR CHECKING OF USE RATE OF REDUNDANCY MEMORY ELEMENT 失效

    公开(公告)号：JPH07254296A

    公开(公告)日：1995-10-03

    申请号：JP30490094

    申请日：1994-12-08

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  MACCARRONE MARCO

    IPC: G11C29/00 ,  G11C29/04

    Abstract: PURPOSE: To provide an integrated circuit for checking the use rate of a redundant memory element inside a semiconductor memory device. CONSTITUTION: A redundant circuit is provided with a programmable nonvolatile memory register 1 for respectively storing the addresses of defective memory elements. When the stored address is coincident with supplied address signals A0-An, a redundant select signal RS is generated. Besides, the signals A0-A1 are supplied to combined circuit means 3 and 9 of the redundant circuit and when a suppress signal DIS' is supplied to the register 1 and the signals A0-An are coincident with the addresses stored in the non-programmed register 1, the generation of the redundant select signal RS is suppressed. When a control signal CHKN is activated, a multiplexer circuit means 11 under the control of the signal CHKN transmits the signal RS to and output pad 17 and when the generation of the signal DIS' is activated, the signal CHKN disturbs that generation.

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