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    TRI-STATE OUTPUT GATE STRUCTURE PARTICULARLY FOR CMOS INTEGRATED CIRCUIT
    11.
    发明专利
    TRI-STATE OUTPUT GATE STRUCTURE PARTICULARLY FOR CMOS INTEGRATED CIRCUIT 失效

    公开(公告)号：JPH04239218A

    公开(公告)日：1992-08-27

    申请号：JP15065091

    申请日：1991-06-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MOLONEY DAVID ,  VAI GIANFRANCO ,  ZUFFADA MAURIZIO ,  BETTI GIORGIO

    IPC: H03K19/0175 ,  H03K19/094 ,  H03K19/0948

    Abstract: PURPOSE: To provide a tri-state output gate structure capable of reducing active inputs and removing or substantially reducing the series connection of plural P-channel transistors(TRs) and allowed to be easily integrated by a CMOS integrated circuit. CONSTITUTION: The structure includes an active terminal 30 for receiving an active signal and an input terminal 31 for receiving an input signal and the input terminal 31 connects an output terminal 32 to a positive power supply terminal or a negative power supply terminal through a signal switching means 38. The active terminal 30 can be electrically connected to the gate terminal of a 1st P-channel TR 33 and the gate terminal of a 2nd N-channel TR 34 through signal inversion means 35, 37. The output terminal 32 is electrically connected to the drain terminals of the 1st and 2nd TRs 33, 34. The 1st and 2nd TRs 33, 34 electrically insulate the output terminal 32 from the input terminal 31.

    13.
    发明专利
    未知

    公开(公告)号：DE69128987D1

    公开(公告)日：1998-04-09

    申请号：DE69128987

    申请日：1991-06-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MOLONEY DAVID ,  VAI GIANFRANCO ,  ZUFFADA MAURIZIO ,  BETTI GIORGIO

    IPC: H03K19/0175 ,  H03K19/094 ,  H03K19/0948

    Abstract: The tristate output gate structure particularly for CMOS integrated circuits comprises an enable terminal (30) receiving an enable signal and an input terminal (31) receiving an input signal, which connects, through signal switching means (38), an output terminal (32) to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor (33) through signal inverting means (35,37) and to the gate terminal of a second N-channel transistor (34). The output terminal (32) is electrically connected to the drain terminals of the first and second transistors (33,34). The first and second transistors (33,34) electrically insulate the output terminal (32) from the input terminal (31).

    15.
    发明专利
    未知

    公开(公告)号：DE69327053D1

    公开(公告)日：1999-12-23

    申请号：DE69327053

    申请日：1993-09-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MOLONEY DAVID ,  GADDUCCI PAOLO ,  BETTI GIORGIO ,  ALINI ROBERTO

    IPC: G11B20/10 ,  G11B20/14 ,  H03M5/06 ,  H03M5/14

    Abstract: In a decoder for decoding a serial data stream, employing an extracted base clock signal, synchronous with an input, coded, serial data stream, a fractionary frequency clock signal for sampling a decoded output data stream and a second fractionary clock signal for synthesizing a pre-decoded value produced by a first combinative logic network within a second combinative logic network to produce a decoded value that is sent to an output sampling flip-flop, a pipelined operation is implemented by momentarily storing the bits that are processed in the second combinative logic network and by anticipating of two full cycles of the synchronous base clock the processing by said first combinative network of the n-number of bits handled by the decoder. Each one of the two combinative logic networks is permitted to complete its decoding process within a full clock cycle in advance of the raising front of the outpunt sampling clock signal. With the same fabrication technology and therefore with the same propagation delay of the two combinative logic networks, the maximum operating spead may be doubled. A limited number of additional components are required to implement the pipelined operation of the invention.

    16.
    发明专利
    未知

    公开(公告)号：DE69323483T2

    公开(公告)日：1999-06-24

    申请号：DE69323483

    申请日：1993-04-06

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BETTI GIORGIO ,  MOLONEY DAVID ,  PORTALURI SALVATORE

    IPC: H03F3/68 ,  H03G1/00 ,  H03G1/04 ,  H03G3/20 ,  H03G3/30 ,  H03G5/16

    Abstract: A variable gain amplifier is composed of a first voltage-to-current amplifier having a fixed gain; a second voltage-to-current amplifier having a variable gain, functioning in parallel to said first amplifier; a gain control and stabilization variable current generator; a current-to-voltage converter. Current output signals produced by said first and second amplifiers and by said variable current generator are summed and the resulting current signal is converted to a voltage signal by said converter.

    18.
    发明专利
    未知

    公开(公告)号：DE69530838D1

    公开(公告)日：2003-06-26

    申请号：DE69530838

    申请日：1995-06-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GADDUCCI PAOLO ,  MOLONEY DAVID ,  BRIANTI FRANCESCO ,  PISATI VALERIO

    IPC: G06F7/02

    Abstract: The invention relates to a basic cell (11) for comparing a first and a second digital signal (A, B), of the type having at least a first and a second input (I1, I2) and a first and a second output (O3, O4) and comprising at least one logic gate (14) receiving digital signals (A, B) at a first and a second signal input (IS1, IS2), and which comprises at least a first and a second controlled switch (P1, P2) inserted in parallel with each other between the output terminal of the logic gate (14) and the second output (O4) from the cell (11), the first switch (P1) being also connected between the first input (I1) and the first output (O3) of the cell (11) and the second switch (P2) being also connected between the second input (I2) and the second output (O4) of the cell (11). The invention also relates to a digital comparator (9) comprising a plurality of basic cells according to the invention.

    20.
    发明专利
    未知

    公开(公告)号：DE69421071T2

    公开(公告)日：2000-04-20

    申请号：DE69421071

    申请日：1994-05-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ZUFFADA MAURIZIO ,  GADDUCCI PAOLO ,  MOLONEY DAVID ,  ALINI ROBERTO

    IPC: G11B5/09 ,  G11B20/10

    Abstract: The device comprises a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel sampling channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two sampling channels (24, 34) comprise, each of them, an analog-digital converter (26, 36) and a Viterbi detector (27, 37) arranged in succession one after the other and operating according to sampling sequences that alternate with one another.

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