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    11.
    发明专利
    未知

    公开(公告)号：DE69627142T2

    公开(公告)日：2003-10-16

    申请号：DE69627142

    申请日：1996-08-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GHILARDELLI ANDREA ,  CAMPARDO GIOVANNI ,  MULATTI JACOPO

    IPC: G11C5/14 ,  G11C16/06

    Abstract: A charge pump comprises at least one charge pump stage (S1-Sn) comprising a first diode (D1-Dn) having an anode (A) and a cathode (K), and a capacitor (C1-Cn) having a first plate connected to the cathode (K) of the diode (D1-Dn) and a second plate connected to a clock signal (CK1,CK2) periodically varying between a reference voltage and a supply voltage (VDD), the anode (A) of said diode (D1-Dn) forming a first terminal (NEG) of the charge pump. The charge pump comprises a second diode (Dn+1) having an anode (A) connected to the cathode (K) of the first diode (D1-Dn) and a cathode (K) forming a second terminal (POS) of the charge pump, first switching means (SW1) for selectively coupling the first terminal (NEG) of the charge pump to the voltage supply (VDD) and second switching means (SW2) for selectively coupling the second terminal (POS) of the charge pump to the reference voltage. The first switching means (SW1) and the second switching means (SW2) are respectively closed and open in a first operating condition whereby the second terminal (POS) of the charge pump acquires a voltage of the same sign but higher in absolute value than said supply voltage (VDD). The first switching means (SW1) and the second switching means (SW2) are respectively open and close in a second operating condition whereby the first terminal (NEG) of the charge pump acquires a voltage of opposite sign with respect to said voltage supply (VDD).

    13.
    发明专利
    未知

    公开(公告)号：DE60130774D1

    公开(公告)日：2007-11-15

    申请号：DE60130774

    申请日：2001-10-25

    Applicant: ST MICROELECTRONICS SRL

    Inventor： LOMAZZI GUIDO ,  MULATTI JACOPO ,  SURICO STEFANO

    IPC: G11C16/10

    Abstract: The programming method includes the following steps: sequentially receiving (23, 27) a plurality of data words; temporarily storing (24, 29) each data word after its reception; and simultaneously writing (31, 35) in parallel the plurality of stored data words in a memory array. After reception and temporary storage of each data word, the memory increments (25) an address counter and sends a "ready" signal (26). Upon reception of each new data word (27), the memory verifies whether the address associated thereto is in the same sector as the initial data word (28) and whether n data words have already been stored (30). If the sector is different, blind-programming step is terminated (35, 36) and the verifying is carried out (37); if the sector is the same but n data words have already been stored temporarily, the memory writes the temporarily stored words in the memory array (31), updates the address counter (25), and then sends the "ready" signal (26).

    14.
    发明专利
    未知

    公开(公告)号：DE69627142D1

    公开(公告)日：2003-05-08

    申请号：DE69627142

    申请日：1996-08-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GHILARDELLI ANDREA ,  CAMPARDO GIOVANNI ,  MULATTI JACOPO

    IPC: G11C5/14 ,  G11C16/06

    Abstract: A charge pump comprises at least one charge pump stage (S1-Sn) comprising a first diode (D1-Dn) having an anode (A) and a cathode (K), and a capacitor (C1-Cn) having a first plate connected to the cathode (K) of the diode (D1-Dn) and a second plate connected to a clock signal (CK1,CK2) periodically varying between a reference voltage and a supply voltage (VDD), the anode (A) of said diode (D1-Dn) forming a first terminal (NEG) of the charge pump. The charge pump comprises a second diode (Dn+1) having an anode (A) connected to the cathode (K) of the first diode (D1-Dn) and a cathode (K) forming a second terminal (POS) of the charge pump, first switching means (SW1) for selectively coupling the first terminal (NEG) of the charge pump to the voltage supply (VDD) and second switching means (SW2) for selectively coupling the second terminal (POS) of the charge pump to the reference voltage. The first switching means (SW1) and the second switching means (SW2) are respectively closed and open in a first operating condition whereby the second terminal (POS) of the charge pump acquires a voltage of the same sign but higher in absolute value than said supply voltage (VDD). The first switching means (SW1) and the second switching means (SW2) are respectively open and close in a second operating condition whereby the first terminal (NEG) of the charge pump acquires a voltage of opposite sign with respect to said voltage supply (VDD).

    17.
    发明专利
    未知

    公开(公告)号：DE69631518D1

    公开(公告)日：2004-03-18

    申请号：DE69631518

    申请日：1996-04-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MACCARRONE MARCO ,  MULATTI JACOPO ,  GOLLA CARLA MARIA

    IPC: G11C16/30 ,  G11C11/00 ,  G11C16/06

    Abstract: A circuit (1) for generating biasing signals in reading of a redundant UPROM cell (2) incorporating at least one memory element (FC) of the EPROM or flash type and having a control terminal (GC) and a conduction terminal (DC) to be biased as well as MOS transistors (M1,M2) connecting said memory element (FC) with a reference low supply voltage (Vcc) comprises a voltage booster (3) for generating at output (U1) a first voltage signal (UGV) to be applied to the control terminal (GC) of the memory element (FC) and a limitation network (5) for said voltage signal (UGV) connected to the output (U1) of the voltage booster (3). There is also provided a circuit portion (10) for generating at output (U2) a second voltage signal (Vb) to be applied to the control terminal of one (M2) of the above mentioned transistors (M1,M2). This circuit portion (10) comprises a timing section (7) interlocked with the voltage booster (3) of a section (8) generating the second voltage signal (Vb).

    19.
    发明专利
    未知

    公开(公告)号：IT1313226B1

    公开(公告)日：2002-06-17

    申请号：ITMI991475

    申请日：1999-07-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MULATTI JACOPO ,  MACCARRONE MARCO

    IPC: G11C5/14 ,  G11C16/12 ,  G11C16/30

    Abstract: Presented is a memory architecture including at least first, second and third voltage booster circuits adapted to generate, on respective first, second and third circuit nodes, at least first, second and third boosted voltage references. These boosted references are in turn connected to first, second and third adjusters, which are adapted to provide respective first, second and third voltage references as required for the operations of programming, erasing and verifying cells of the memory architecture. At least a first switch block is used that connects between the first and third circuit nodes and is controlled by a first control signal to place the first and third high-voltage references in parallel during cell verify operations, thereby to provide one equivalent high-voltage source having a higher capacity for current than individual sources and effectively speed up the charging of the first circuit node so as to shorten the settling time of the first voltage reference. A method is also presented for generating voltage references with a reduced value of settling time as produced within a memory architecture.

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