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19 records (took 0.021 seconds)

    11.
    发明专利
    未知

    公开(公告)号：IT1319037B1

    公开(公告)日：2003-09-23

    申请号：ITMI20002337

    申请日：2000-10-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  GREGORI STEFANO ,  PIERIN ANDREA ,  MICHELONI RINO ,  CORONINI SERGIO ,  TORELLI GUIDO

    IPC: G11C7/06 ,  G11C11/56 ,  G11C16/28 ,  G11C27/00

    Abstract: A circuit for reading a non-volatile memory cell has an output terminal for providing an output current, and a control terminal for receiving a voltage for controlling the output current. The reading circuit includes a feedback circuit which can be connected electrically to the output terminal and to the control terminal to generate the control voltage from a reference signal and from the output current. The feedback circuit also includes a current-amplification circuit having a first terminal for receiving a current-error signal derived from the reference signal and from the output current, and a second terminal for supplying an amplified current.

    12.
    发明专利
    未知

    公开(公告)号：IT1318158B1

    公开(公告)日：2003-07-23

    申请号：ITMI20001585

    申请日：2000-07-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  PIERIN ANDREA ,  MICHELONI RINO ,  GREGORI STEFANO ,  TORELLI GUIDONO ,  SANGALLI MIRIAM

    IPC: G11C16/08

    Abstract: A circuit device for performing hierarchic row decoding in semiconductor memory devices of the non-volatile type, which memory devices include an array of memory cells with column-ordered sectors, wherein each sector has a respective group of local wordlines linked to a main wordline. The circuit device includes a main wordline driver provided at each main wordline, and a local decoder provided at each local wordline. This circuit device further comprises, for each main wordline, a dedicated path connected between the main wordline and the local decoders of the associated local wordlines and connected to an external terminal arranged to receive a read/program voltage, the dedicated path enabling transfer of the read/program voltage to the local decoders.

    13.
    发明专利
    未知

    公开(公告)号：ITMI20002337A1

    公开(公告)日：2002-04-29

    申请号：ITMI20002337

    申请日：2000-10-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： TORELLI GUIDO ,  MICHELONI RINO ,  KHOURI OSAMA ,  PIERIN ANDREA ,  GREGORI STEFANO ,  CORONINI SERGIO

    IPC: G11C7/06 ,  G11C11/56 ,  G11C16/28 ,  G11C27/00

    Abstract: A circuit for reading a non-volatile memory cell has an output terminal for providing an output current, and a control terminal for receiving a voltage for controlling the output current. The reading circuit includes a feedback circuit which can be connected electrically to the output terminal and to the control terminal to generate the control voltage from a reference signal and from the output current. The feedback circuit also includes a current-amplification circuit having a first terminal for receiving a current-error signal derived from the reference signal and from the output current, and a second terminal for supplying an amplified current.

    14.
    发明专利
    未知

    公开(公告)号：DE60139670D1

    公开(公告)日：2009-10-08

    申请号：DE60139670

    申请日：2001-04-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GREGORI STEFANO ,  MICHELONI RINO ,  PIERIN ANDREA ,  KHOURI OSAMA ,  TORELLI GUIDO

    IPC: G11C16/02 ,  G11C16/12 ,  G11C11/56

    Abstract: The method involves applying in succession, to a control terminal of the memory cell, at least two programming pulse trains (F1,F2) with pulse amplitude increasing in staircase fashion. The amplitude increment between one pulse and the next in the first programming pulse train (F1) is greater than the amplitude increment between one pulse and the next in the second programming pulse train (F2). Transition from the first programming pulse to train to the second is made when the memory cell has a threshold voltage with a pre-set relation with a reference value.

    17.
    发明专利
    未知

    公开(公告)号：DE69823982D1

    公开(公告)日：2004-06-24

    申请号：DE69823982

    申请日：1998-05-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MANSTRETTA ALESSANDRO ,  PIERIN ANDREA ,  TORELLI GUIDO

    IPC: G11C16/06 ,  G11C16/04 ,  G11C16/12

    Abstract: A selector switch monolithically integrated to a CMOS technology circuit for electrically programmable memory cell devices having at least first and second input terminals for coupling to first and second voltage generators (HV and LV), respectively, and an output terminal (OUT). First (P1) and second (P2) field-effect selection transistors are respectively connected, via first and second terminals, between the first input terminal and the output terminal and between the second input terminal and the output terminal. These transistors are driven through control terminals at non-overlapping phases and have body terminals connected at a body circuit node (BODY) which is coupled to the first and second voltage generators through a bias circuit block (WBC) effective to bias the node to the higher of the instant voltages generated by the first and second generators.

    19.
    发明专利
    未知

    公开(公告)号：ITTO20000936D0

    公开(公告)日：2000-10-06

    申请号：ITTO20000936

    申请日：2000-10-06

    Applicant: ST MICROELECTRONICS SRL

    Inventor： TORELLI GUIDO ,  MICHELONI RINO ,  PIERIN ANDREA ,  GREGORI STEFANO ,  KHOURI OSAMA

    IPC: G11C11/56 ,  G11C16/26 ,  G11C16/30

    Abstract: A multilevel nonvolatile memory includes a supply line (28) supplying a supply voltage (VDD), a voltage boosting circuit (26) supplying a boosted voltage (Vp), higher than the supply voltage (VDD), a boosted line (30) connected to the voltage boosting circuit (26) and a reading circuit (25) including at least one comparator (35). The comparator (35) includes a first and a second input (35a, 35b), a first and a second output (45a, 45b), at least one amplification stage (40) connected to the boosted line (30), and a boosted line latch stage (41) connected to the supply line (28).

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