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公开(公告)号：ITTO990993A1
公开(公告)日：2001-05-16
申请号：ITTO990993
申请日：1999-11-16
Applicant: ST MICROELECTRONICS SRL
Inventor： KHOURI OSAMA , MICHELONI RINO , SACCO ANDREA , TORELLI GUIDO
Abstract: A voltage generator formed of a charge circuit and a discharge circuit having a common programmable voltage divider with variable resistance; the programmable voltage divider including a plurality of resistors arranged in series and selectively connectable to define alternatively a step-wise increasing program voltage and a fixed verify voltage. The charge circuit formed of a voltage regulator supplying at the output the precise voltage value determined by the programmable voltage divider, and the discharge circuit intervening when the output voltage must be switched in a controlled manner from a higher value to a lower value.
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公开(公告)号：DE69937559T2
公开(公告)日：2008-10-23
申请号：DE69937559
申请日：1999-09-10
Applicant: ST MICROELECTRONICS SRL
Inventor： MICHELONI RINO , SACCO ANDREA , MOGNONI SABINA
IPC: G01R31/02 , G11C29/00 , G01R31/28 , G01R31/30 , G01R31/319 , G11C17/00 , G11C29/02 , G11C29/12 , G11C29/50
Abstract: The non volatile memory device integrates, in one and the same chip (100), the array (2) of memory cells, a voltage regulator (REG) which supplies a regulated operating voltage (Vr) to a selected word line (LWL1), and a short circuit detecting circuit (10). The short circuit detecting circuit detects the output voltage (IM1) of the voltage regulator (REG), which is correlated to the current (Iw) for biasing the cells (3) of the word line selected (LWL1). Once settled to the steady state condition, the output current (IM1) assumes one first value (IM1') in the absence of short circuits, and one second value (IM1") in the presence of a short circuit between the word line selected (LWL1) and one or more adjacent word lines (LWL0, LWL2, ..., LWLn). The short circuit detecting circuit (10) compares the output current (IM1) of the voltage regulator (REG) with a reference value (Iref) and generates at output a short circuit digital signal (Vo) which indicates the presence or otherwise of a short circuit.
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公开(公告)号：IT1314178B1
公开(公告)日：2002-12-04
申请号：ITTO990798
申请日：1999-09-17
Applicant: ST MICROELECTRONICS SRL
Inventor： MICHELONI RINO , SACCO ANDREA , SCOTTI MARCO
IPC: H03K19/003
Abstract: A circuit for biasing the bulk terminal of a first MOS transistor having a first terminal connected to a first line set to a first potential, and a second terminal connected to a second line set to a second potential. The biasing circuit includes a second and a third MOS transistors having first terminals connected respectively to the first line and to the second line, second terminals connected to the bulk terminal of the first MOS transistor, and control terminals connected respectively to the second and to the first line.
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公开(公告)号：ITMI20002367A1
公开(公告)日：2002-05-01
申请号：ITMI20002367
申请日：2000-10-31
Applicant: ST MICROELECTRONICS SRL
Inventor： MICHELONI RINO , SACCO ANDREA
Abstract: A pulse programming method for a non-volatile memory device includes: addressing memory cells to be programmed within the device by selecting corresponding hierarchic decoder transistors; biasing the gate terminals of the memory cells; and programming the memory cells by applying a voltage pulse, regulated by a bias circuit, to the drain terminals of the memory cells. Advantageously, the programming method further comprises a step of precharging an internal node of the bias circuit before starting the programming step, the internal node being connected to a parasitic capacitance of the memory device.
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公开(公告)号：ITTO990798A1
公开(公告)日：2001-03-19
申请号：ITTO990798
申请日：1999-09-17
Applicant: ST MICROELECTRONICS SRL
Inventor： MICHELONI RINO , SACCO ANDREA , SCOTTI MARCO
IPC: H03K19/003
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Patent Agency Ranking
公开(公告)号：ITTO20000892D0
公开(公告)日：2000-09-22
申请号：ITTO20000892
申请日：2000-09-22
Applicant: ST MICROELECTRONICS SRL
Inventor： SACCO ANDREA , KHOURI OSAMA , TORELLI GUIDO , MICHELONI RINO
Abstract: Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.
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公开(公告)号：ITTO990993D0
公开(公告)日：1999-11-16
申请号：ITTO990993
申请日：1999-11-16
Applicant: ST MICROELECTRONICS SRL
Inventor： KHOURI OSAMA , MICHELONI RINO , SACCO ANDREA , TORELLI GUIDO
Abstract: A voltage generator formed of a charge circuit and a discharge circuit having a common programmable voltage divider with variable resistance; the programmable voltage divider including a plurality of resistors arranged in series and selectively connectable to define alternatively a step-wise increasing program voltage and a fixed verify voltage. The charge circuit formed of a voltage regulator supplying at the output the precise voltage value determined by the programmable voltage divider, and the discharge circuit intervening when the output voltage must be switched in a controlled manner from a higher value to a lower value.
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公开(公告)号：DE69927364D1
公开(公告)日：2005-10-27
申请号：DE69927364
申请日：1999-07-28
Applicant: ST MICROELECTRONICS SRL
Inventor： MICHELONI RINO , KHOURI OSAMA , SACCO ANDREA , PICCA MASSIMILIANO
Abstract: The memory device (10) comprises a memory array (2) having an organisation of the type comprising global word lines (4) and local word lines (6), a global row decoder (8) addressing the global word lines (4), a local row decoder (12) addressing the local word lines (6), a global power supply stage (22) supplying the global row decoder (8), and a local power supply stage (24) supplying the local row decoder (12).
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公开(公告)号：IT1306964B1
公开(公告)日：2001-10-11
申请号：ITMI990081
申请日：1999-01-19
Applicant: ST MICROELECTRONICS SRL
Inventor： MICHELONI RINO , KHOURI OSAMA , MOTTA ILARIA , SACCO ANDREA , TORELLI GUIDO
Abstract: A circuit for the regulation of the word line voltage in a memory, comprising a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more word lines of the memory when the one or more word lines are being selected. The circuit includes a voltage boosting circuit that is coupled to the output of said voltage regulator and that can be activated upon the selection of one or more memory word lines in order to boost the regulated voltage upon the selection of the one or more memory word lines.
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公开(公告)号：ITMI990081A1
公开(公告)日：2000-07-19
申请号：ITMI990081
申请日：1999-01-19
Applicant: ST MICROELECTRONICS SRL
Inventor： MICHELONI RINO , KHOURI OSAMA , MOTTA ILARIA , SACCO ANDREA , TORELLI GUIDO
Abstract: A circuit for the regulation of the word line voltage in a memory, comprising a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more word lines of the memory when the one or more word lines are being selected. The circuit includes a voltage boosting circuit that is coupled to the output of said voltage regulator and that can be activated upon the selection of one or more memory word lines in order to boost the regulated voltage upon the selection of the one or more memory word lines.
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