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    LAYOUT OF REDUNDANCY CIRCUIT FOR SEMICONDUCTOR MEMORY
    12.
    发明专利
    LAYOUT OF REDUNDANCY CIRCUIT FOR SEMICONDUCTOR MEMORY 失效

    公开(公告)号：JPH08102527A

    公开(公告)日：1996-04-16

    申请号：JP6925895

    申请日：1995-03-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  CARRERA MARCELLO ,  DEFENDI MARCO

    IPC: G11C17/00 ,  G11C5/02 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10

    Abstract: PURPOSE: To provide the layout of a redundancy circuit, wherein the chip area required for realization of redundancy becomes a minimum area. CONSTITUTION: An array MAR of a programmable nonvolatile memory, which stores a redundancy bit line, a redundancy word line, a defective bit line, which should be functionally replaced respectively, and the address of a word line is provided. The layout of the redundancy circuit is divided into a plurality of the same layout strips LS1-LS4, which intersect the array at right angles and have first and second strip parts at both sides of the array. The first strip part intersects a column-address signal bus CABUS, extending in parallel with the array. The second strip part intersects a row-address signal bus (RABUS), extending in parallel with the array.

    READ TIMING METHOD OF NONVOLATILE MEMORY AND CIRCUIT
    13.
    发明专利
    READ TIMING METHOD OF NONVOLATILE MEMORY AND CIRCUIT 失效

    公开(公告)号：JPH0855485A

    公开(公告)日：1996-02-27

    申请号：JP4796295

    申请日：1995-02-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  PADOAN SILVIA ,  GOLLA CARLA MARIA ,  MACCARRONE MARCO ,  OLIVO MARCO

    IPC: G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C16/06

    Abstract: PURPOSE: To derive optimum performance from a memory by enabling the circuit with a switching edge, making the circuit programmable, and protecting the circuit against noise. CONSTITUTION: A delay unit 23 inputs a low-level signal, which goes up to a high level a delay time corresponding to the contents of memory elements 20 and 22 after a leading edge of a signal ATD is received, to a NOR gate 27. The gate 27 inputs a signal PC as a signal DET to an asymmetrical delay unit 24 through a NOR gate 28, and a low-level data simulation signal SP is outputted which goes up to the high level a delay time based upon the elements 20 and 21 after a leading edge of the signal DET is received. The signal SP is transferred to an output similar circuit 33 and at its completion time, a high level is outputted. Consequently, signals N and L are switched to the low level and the output STP of a continuance expanding circuit 51 goes down to a low level. Consequently, the data loading is completed. This loading lasts accurately in an output circuit 108 during data propagation.

    GENERATING METHOD OF LOAD SIGNAL TO NONVOLATILE MEMORY AND CIRCUIT THEREOF
    17.
    发明专利
    GENERATING METHOD OF LOAD SIGNAL TO NONVOLATILE MEMORY AND CIRCUIT THEREOF 失效

    公开(公告)号：JPH0863953A

    公开(公告)日：1996-03-08

    申请号：JP4930295

    申请日：1995-02-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  GOLLA CARLA MARIA

    IPC: G11C17/00 ,  G11C5/14 ,  G11C7/00 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C16/06

    Abstract: PURPOSE: To obtain a load signal generating method and circuit for a non- volatile memory. CONSTITUTION: A circuit 1 is used to generate a variable length data load pulse L depending on the requirement and is provided with a source 5 for applying a short load signal SP and a delay element 19 for generating a long pulse STP when the short load signal appears. Static operation mode is given so that a load pulse is generated continuously through the static operation so long as the critical state (standby condition, low voltage) is continued. An expanded pulse is always generated when the static operation mode terminates, while a delay element 19 is disabled by a command EN when the expanded timing is not required.

    INTERNAL TIMING METHOD TO REWRITABLE MEMORY AND CIRCUIT THEREOF
    20.
    发明专利
    INTERNAL TIMING METHOD TO REWRITABLE MEMORY AND CIRCUIT THEREOF 失效

    公开(公告)号：JPH0896569A

    公开(公告)日：1996-04-12

    申请号：JP5038495

    申请日：1995-02-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO ,  GOLLA CARLA MARIA

    IPC: G11C17/00 ,  G11C7/00 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C16/06

    Abstract: PURPOSE: To obtain an internal timing method to a rewritable memory and a circuit thereof. CONSTITUTION: A circuit 1 generates slow or fast overall timing configuration and flexible timing enabling the two configuration of pre-charge and detection intervals by giving the levels of two short and long periods. For conduct the generation of the timing, variable asymmetric propagation lines 5, 37 consisting of a series of basic delay elements 6-8, 38, 40 bringing data to an enable or disenable state on the basis of logical signals TIMS, PCS, and DETS stored are contained in the circuit 1, and the state is determined when a memory 100 executed by the circuit is debugged.

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