Process for the manufacturing of a SOI wafer by oxidation of buried cavities
    15.
    发明公开
    Process for the manufacturing of a SOI wafer by oxidation of buried cavities 审中-公开
    一种用于通过掩埋空腔氧化来制造SOI晶片工艺

    公开(公告)号:EP1073112A1

    公开(公告)日:2001-01-31

    申请号:EP99830477.8

    申请日:1999-07-26

    CPC classification number: H01L21/76248 H01L21/76208

    Abstract: The process comprises the steps of forming, in a wafer (200) of monocrystalline silicon, first trenches extending between portions of the wafer; etching the substrate (90) to remove the silicon around the first trenches and forming cavities (121) in the substrate (90); covering the walls of the cavities with an epitaxial growth inhibiting layer; growing a monocrystalline epitaxial layer (126) on top of the substrate (90) and the cavities so as to obtain a monocrystalline wafer embedding buried cavities completely surrounded by silicon; forming second trenches (144) extending in the epitaxial layer (126) as far as the cavities; removing the epitaxial growth inhibiting layer; oxidizing the cavities, forming at least one continuous region (127) of buried oxide; depositing a polysilicon layer on the entire surface of the wafer and inside the second trenches (144); removing the polysilicon layer on the surface, leaving filling regions (148) inside the second trenches (144); oxidizing, on the top, portions of said filling regions so as to form field oxide regions (150).

    Abstract translation: 该方法包括形成的步骤中,在单晶硅,第一沟槽的晶片的部分之间延伸的一个晶片(200); 在基片蚀刻所述衬底(90),以去除围绕所述第一沟槽中的有机硅和形成空腔(121)(90); 覆盖所述腔的壁与在外延生长抑制层; 在基板(90)和所述腔的顶部生长单晶外延层(126),以便获得一个单晶晶片埋嵌入空腔完全通过呼叫硅包围; 形成第二沟槽(144)在所述外延层(126)延伸尽可能所述空腔; 除去外延生长抑制层; 氧化所述空腔中,形成埋入氧化物中的至少一个连续区域(127); 沉积所述第二沟槽内的晶片的表面上的多晶硅层和整个(144); 所述第二沟槽内的表面上去除所述多晶硅层,留下填充区(148)(144); 氧化性,在上面,所述填充区域的部分,以形成场氧化区(150)。

    Isotropic etching of silicon using hydrogen chloride
    16.
    发明公开
    Isotropic etching of silicon using hydrogen chloride 审中-公开
    IsotropesÄtzenvon Silizium mittelsSalzsäure

    公开(公告)号:EP1001458A1

    公开(公告)日:2000-05-17

    申请号:EP98830673.4

    申请日:1998-11-09

    CPC classification number: H01L21/3065

    Abstract: The subject of the present invention is a method of forming isotropic recesses in a silicon "wafer".
    In particular, the present invention relates to a method for isotropic etching of a silicon wafer, comprising the steps of:

    providing a silicon wafer having a protective mask of silicon nitride,
    putting the silicon wafer into contact with gaseous hydrogen chloride.

    Abstract translation: 本发明的主题是在硅“晶片”中形成各向同性的凹槽的方法。 特别地,本发明涉及一种用于硅晶片的各向同性蚀刻的方法,包括以下步骤:提供具有氮化硅保护掩模的硅晶片,使硅晶片与气态氯化氢接触。

    A method for manufacturing an SO1 wafer
    17.
    发明公开
    A method for manufacturing an SO1 wafer 失效
    Herstellung einer SO1-Scheibe的Ein Verfahren

    公开(公告)号:EP0948034A1

    公开(公告)日:1999-10-06

    申请号:EP98830206.3

    申请日:1998-04-03

    CPC classification number: H01L21/3065 H01L21/76248 H01L21/76294

    Abstract: The method includes the steps of: on a wafer (1) of monocrystalline semiconductor material, forming a hard mask (9') of an oxidation-resistant material, defining first protective regions (7) covering first portions (21) of the wafer (1); and forming first trenches (10'') in the wafer (1). The first trenches are formed by two etching steps: firstly, the portions (8'') of the wafer (1) not covered by the hard mask (9') are isotropically etched, such as to remove the semiconductor material not only from the portions without a mask, but also partially below the first protective regions (7); then anisotropic etching is carried out. After forming second protective regions (30) incorporating the first protective regions (7), final trenches (16) are formed, and the semiconductor material of wafer (1) is oxidised, except for the portions (21) which are covered by the second protective regions (30), in order to form a continuous oxide region (22); after removal of the second protective regions (30), a monocrystalline layer (23) is grown epitaxially from the non-oxidised portions (21).

    Abstract translation: 该方法包括以下步骤:在单晶半导体材料的晶片(1)上形成抗氧化材料的硬掩模(9'),限定覆盖晶片的第一部分(21)的第一保护区域(7) 1); 以及在所述晶片(1)中形成第一沟槽(10“)。 第一沟槽由两个蚀刻步骤形成:首先,未被硬掩模(9')覆盖的晶片(1)的部分(8“)被各向同性地蚀刻,例如不仅从 没有掩模的部分,但也部分地在第一保护区域(7)下面; 然后进行各向异性蚀刻。 在形成并入有第一保护区域(7)的第二保护区域(30)之后,形成最终沟槽(16),并且晶片(1)的半导体材料被氧化,除了由第二保护区域 保护区域(30),以形成连续氧化物区域(22); 在除去第二保护区域(30)之后,从非氧化部分(21)外延生长单晶层(23)。

    Fluidic cartridge for detecting chemicals in samples, in particular for performing biochemical analyses
    18.
    发明公开
    Fluidic cartridge for detecting chemicals in samples, in particular for performing biochemical analyses 审中-公开
    流体盒用于检测样品中的化学物质,特别是用于进行生化分析

    公开(公告)号:EP2399672A2

    公开(公告)日:2011-12-28

    申请号:EP11171813.6

    申请日:2011-06-28

    Abstract: A fluidic cartridge (35; 135) for detecting chemicals, formed by a casing (40; 140), hermetically housing an integrated device (20) having a plurality of detecting regions (22) to bind with target chemicals; part of a supporting element (41; 141), bearing the integrated device; a reaction chamber (65; 165), facing the detecting regions (22); a sample feeding hole (50, 51; 150) and a washing feeding hole (52; 152), self-sealingly closed; fluidic paths (63, 64, 70, 71; 163, 164, 170, 171), which connect the sample feeding and washing feeding holes (50-52; 150, 152) to the reaction chamber (65; 165); and a waste reservoir (80; 180), which may be fluidically connected to the reaction chamber by valve elements (82, 76; 182, 176) that may be controlled from outside. The integrated device is moreover connected to an interface unit (42) carried by the supporting element (41; 141), electrically connected to the integrated device and including at least one signal processing stage and external contact regions (75; 175).

    Abstract translation: 甲流体盒(35; 135),用于检测化学品,由壳体(40; 140)形成为具有探测区域(22)多个与靶化学物质结合,气密壳体集成装置(20); ,轴承集成装置;一个支撑元件(141 41)的一部分; 面向所述检测区域(22);一个反应室(165 65); 一个样品进料孔(50,51; 150)和一洗涤进料孔(52; 152),自密封地关闭; 流体通路(63,64,70,71; 163,164,170,171),连接所述进样和洗涤进料孔(50-52; 150,152)到所述反应室(65; 165); 和废物容器(80; 180),其可被流体地连接到由阀元件在反应室(82,76; 182,176),并可以从外部进行控制。 集成器件是在多个连接到在由支撑元件所承载接口单元(42)(41; 141),电连接到所述集成器件和包括至少一个信号处理级和外部接触区域(75; 175)。

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