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    Non-volatile memory with functional capability of burst mode read and page mode read during suspension of an operation of electrical alteration.
    12.
    发明公开
    Non-volatile memory with functional capability of burst mode read and page mode read during suspension of an operation of electrical alteration. 审中-公开
    该悬浮液的电变化效果期间的突发和页模式读取功能能力的非易失性存储器

    公开(公告)号：EP1073063A1

    公开(公告)日：2001-01-31

    申请号：EP99830494.3

    申请日：1999-07-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bartoli, Simone ,  Bedarida, Lorenzo ,  Sali, Mauro ,  Russo, Antonio

    IPC: G11C16/10 ,  G11C16/26

    CPC classification number: G11C16/26 ,  G11C16/10 ,  G11C2216/20

    Abstract: An electrically alterable semiconductor memory comprises at least two memory sectors (S1-S9) the content of which is individually alterable, and first control circuit means (4, 6) for controlling operations of electrical alteration of the content of the memory, capable of permitting the selective execution of an operation of electrical alteration of the content of one of said at least two memory sectors with the possibility of suspending said execution in order to permit read access to the other of said at least two memory sectors. The memory comprises second control circuit means (8, 6) capable of permitting, during said suspension, an operation of burst mode or page mode reading of the content of the other memory sector.

    Abstract translation: 电可变半导体存储器包括至少两个存储器扇区（S1-S9）的所有其是独立可变的内容，以及第一控制电路装置（4,6），用于控制所述存储器的内容的电改变的操作，能够允许的 的操作的所述一个的所述内容的电改变的至少两个存储器扇区选择性执行，以便暂停所述执行的可能性，以允许读访问另一所述的至少两个存储器扇区。 所述存储器包括第二控制电路装置能够允许，所述悬浮液期间的突发模式或其他存储器扇区的内容的页面模式读取手术的（8,6）。

    Autotesting method of a memory cells matrix, particularly of the non-volatile type
    15.
    发明公开
    Autotesting method of a memory cells matrix, particularly of the non-volatile type 审中-公开
    Verfahren zum Selbstest einer Speichermatrix，insbesondere einesnichtflüchtigenSpeichers

    公开(公告)号：EP1324348A1

    公开(公告)日：2003-07-02

    申请号：EP01830832.0

    申请日：2001-12-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Geraci, Antonino ,  Campisi, Alberto ,  Bedarida, Lorenzo ,  Bartoli, Simone

    IPC: G11C29/00

    CPC classification number: G11C29/44

    Abstract: An autotesting method of a cells matrix of a memory device is disclosed which comprises the steps of:

    reading the values contained in a plurality of the memory cells;
    comparing the read values with reference values;
    signalling mismatch of the read values with the reference values as an error situation; and
    storing the error situations.

    In the autotesting method, the reading, comparing, signalling, and storing steps are repeated for all the memory cells in an matrix column.
    The autotesting method according to the invention further comprises the steps of:

    storing the addresses of any columns having at least one error situation; and
    repeating all the preceding steps according to a step of scanning all the matrix columns.

    Advantageously according to the invention, all said steps are internally realized in the memory device.
    Also disclosed is a memory device with a autotesting architecture, which device is adapted to implement the autotesting method according to the invention.

    Abstract translation: 公开了一种存储器件的单元矩阵的自动测试方法，其包括以下步骤：读取多个存储器单元中包含的值; 将读取的值与参考值进行比较; 将读取值与参考值的信令不匹配作为错误情况; 并存储错误情况。 在自动测试方法中，对矩阵列中的所有存储单元重复读取，比较，信令和存储步骤。 根据本发明的自动测试方法还包括以下步骤：存储具有至少一个错误情况的任何列的地址; 并且根据扫描所有矩阵列的步骤重复所有前述步骤。 有利地，根据本发明，所有所述步骤在内部实现在存储器件中。 还公开了具有自动测试架构的存储器件，该器件适于实现根据本发明的自动测试方法。

    High configurability output-buffer circuit
    16.
    发明公开
    High configurability output-buffer circuit 审中-公开
    Hochkonfigurierbare Ausgangspufferschaltung

    公开(公告)号：EP1221771A1

    公开(公告)日：2002-07-10

    申请号：EP01830005.3

    申请日：2001-01-08

    Applicant: STMicroelectronics S.r.l.

    Inventor： Sforzin, Marco ,  Bedarida, Lorenzo ,  Defendi, Marco ,  Nava, Claudio

    IPC: H03K17/16

    CPC classification number: H03K19/00361 ,  H03K17/163

    Abstract: The output-buffer circuit (1) comprises an end stage (2) made up of a pull-up transistor (3) and a pull-down transistor (4) connected in series between a supply line (5) and a ground line (GND); a first driving stage (8) connected to a control terminal of the pull-up transistor (3) and comprising a plurality of first driving branches (12) which can be selectively activated by a logic control circuit (16) according to the reading and operating modes of a memory device (100) including the output-buffer circuit (1) and to the variability of the electrical parameters of the output-buffer circuit; and a second driving stage (9) connected to a control terminal of the pull-down transistor (4) and comprising a plurality of second driving branches (22) which can also be selectively activated by the control circuit (16) according to the reading and operating modes of a memory device (100) including the output-buffer circuit (1) and to the variability of the electrical parameters of the output-buffer circuit.

    Abstract translation: 输出缓冲电路（1）包括由串联连接在电源线（5）和接地线（5）之间的上拉晶体管（3）和下拉晶体管（4）构成的端级（2） GND）; 第一驱动级（8），连接到所述上拉晶体管（3）的控制端，并且包括多个第一驱动分支（12），所述第一驱动分支可根据所述读取被逻辑控制电路（16）选择性地激活;以及 包括输出缓冲器电路（1）的存储器件（100）的工作模式以及输出缓冲器电路的电气参数的可变性; 以及连接到所述下拉晶体管（4）的控制端子并且包括多个第二驱动分支（22）的第二驱动级（9），所述第二驱动分支（22）还可以根据所述读取被所述控制电路（16）选择性地启动 以及包括输出缓冲器电路（1）的存储器件（100）的工作模式以及输出缓冲器电路的电气参数的变化。

    Non-volatile memory device with burst mode reading and corresponding reading method
    17.
    发明公开
    Non-volatile memory device with burst mode reading and corresponding reading method 有权
    NichtflüchtigerSpeicher mit Burstlesebetrieb sowie entsprechendes Leseverfahren

    公开(公告)号：EP1103978A1

    公开(公告)日：2001-05-30

    申请号：EP99830723.5

    申请日：1999-11-25

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bartoli, Simone ,  Geraci, Antonino ,  Sali, Mauro ,  Bedarida, Lorenzo

    IPC: G11C7/00

    CPC classification number: G11C7/1072 ,  G11C7/1033 ,  G11C7/1045

    Abstract: The invention relates to a read control circuit portion (1) and an attendant reading method for an electronic memory device (2) integrated in a semiconductor and including a non-volatile memory matrix (4) with associated row and column decoders (5,6) connected to respective outputs of an address counter (7), an ATD circuit (12) for detecting an input transaction as the memory device is being accessed, and read amplifiers (8) and attendant registers (10) for transferring the data read from the memory (2) to the output. The control circuit portion (1) comprises a detection circuit block (15) which is input a clock signal (CK) and a logic signal (BAN) to enable reading in the burst mode, and a burst read mode control logic (3) connected downstream of the circuit block (15).
    The method of this invention comprises accessing the memory matrix in a random read mode; detecting a request for access in the burst read mode; and executing the parallel reading of a plurality of memory words during a single period of time clocked by a clock signal (CK).

    Abstract translation: 本发明涉及集成在半导体中并且包括具有相关行和列解码器（5,6）的非易失性存储器矩阵（4）的电子存储器件（2）的读控制电路部分（1）和辅助读取方法 ），连接到地址计数器（7）的各个输出的ATD电路（12），用于检测作为存储器件被访问的输入事务的ATD电路（12），以及读取放大器（8）和从站寄存器（10） 存储器（2）输出。 控制电路部分（1）包括检测电路块（15），其输入时钟信号（CK）和逻辑信号（BAN）以使能在突发模式下进行读取，并且连接脉冲串读取模式控制逻辑（3） 在电路块（15）的下游。 本发明的方法包括以随机读取模式访问存储矩阵; 在突发读取模式下检测访问请求; 以及在由时钟信号（CK）计时的单个时间段内执行多个存储字的并行读取。

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