公开(公告)号：EP1601113A1

公开(公告)日：2005-11-30

申请号：EP04425375.5

申请日：2004-05-25

Applicant: STMicroelectronics S.r.l.

Inventor： Nicollini, Germano ,  Confalonieri, Pierangelo ,  Martignone, Riccardo

IPC: H04B1/707

CPC classification number: H04B1/707

Abstract: There is described a wide-band transmission system, particularly for employment in cellular telephony systems that adopt the WCDMA standard. The system comprises means for generating two digital signals containing information to be transmitted, means for converting into analog form the two signals comprising, for each signal to be converted, a digital-analog converter (DAC) followed by a low-pass filter (LOW-PASS), means for modulating both in phase and in quadrature a radio frequency carrier with the two signals issuing from the low-pass filters (LOW-PASS), and means for transmitting the modulated carrier in accordance with a predetermined emission mask. If the system is to be capable of being integrated into an area of small extent and is to have a low current consumption, the low-pass filter (LOW-PASS) is an active filter of the second order continuous in time and current-coupled to the output of the digital-analog converter (DAC) and the digital-analog converter (DAC) is a converter of the current-steering type functioning at a sampling frequency greater than the Nyquist frequency by at least as much as is necessary to respect the predetermined emission mask.

Abstract translation: 描述了一种宽带传输系统，特别是在采用WCDMA标准的蜂窝电话系统中的就业。 该系统包括用于产生包含要发送的信息的两个数字信号的装置，用于将两个信号转换成模拟形式的装置，对于每个要转换的信号，包括数模转换器（DAC）和随后的低通滤波器（LOW -PASS），用于利用从低通滤波器（LOW-PASS）发出的两个信号同时和正交调制无线电频率载波的装置，以及用于根据预定的发射掩模传送调制载波的装置。 如果系统能够集成到小范围的区域并且具有低电流消耗，则低通滤波器（LOW-PASS）是时间上连续的二阶有源滤波器和电流耦合 数字模拟转换器（DAC）的输出端和数模转换器（DAC）是以大于奈奎斯特频率的采样频率工作的电流导向型转换器，其至少必须相当于必须的 预定的发射掩模。

公开(公告)号：EP1217744A1

公开(公告)日：2002-06-26

申请号：EP00830836.3

申请日：2000-12-21

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Nagari, Angelo ,  Nicollini, Germano

IPC: H03K19/003 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/00 ,  H03K19/017 ,  G11C7/10

CPC classification number: G11C7/1051 ,  H03K19/00361

Abstract: The buffer has an output stage (10) formed by two complementary MOS transistors (MPOUT, MNOUT) connected so as to operate in phase opposition between the supply terminals (VDD, earth) and two driver stages (14 and 15) having the input (IN) in common. Each driver stage (14, 15) has a first branch comprising a current-generator (MN4, MP4) connected between the gate electrode of the transistor to be driven (MPOUT, MNOUT) and a supply terminal (earth, VDD) and an electronic switch (MP1, MN1) controlled by the input (IN) and connected between the same gate electrode and the other supply terminal (VDD, earth), and a second branch which comprises, connected in series, a transistor connected as a diode (MP3, MN3) and an electronic switch (MP2, MN2) controlled by the output (OUT), and is arranged between the gate electrode of the transistor to be driven (MPOUT, MNOUT) and a respective supply terminal (VDD, earth). The buffer can control a load (13) with a constant switching current, is simple in structure, and occupies a small area.

Abstract translation: 缓冲器具有由两个互补MOS晶体管（MPOUT，MNOUT）形成的输出级（10），以在电源端子（VDD，接地）和具有输入端的两个驱动器级（14和15）之间相对操作， IN）的共同点。 每个驱动器级（14,15）具有第一分支，包括连接在待驱动晶体管（MPOUT，MNOUT）的栅电极和电源端（地，VDD）之间的电流发生器（MN4，MP4）和电子 开关（MP1，MN1）由输入（IN）控制并连接在同一个栅极和另一个电源端子（VDD，接地）之间，第二个分支包括串联连接为二极管的晶体管（MP3 ，MN3）和由输出（OUT）控制的电子开关（MP2，MN2），并且被布置在待驱动晶体管（MPOUT，MNOUT）的栅电极和相应的电源端子（VDD，接地）之间。 缓冲器可以用恒定的开关电流控制负载（13），结构简单，占用面积小。

公开(公告)号：EP2023392A1

公开(公告)日：2009-02-11

申请号：EP07425517.5

申请日：2007-08-08

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Martignone, Riccardo ,  Pernici, Sergio

IPC: H01L27/02

CPC classification number: H01L27/0288

Abstract: Integrated circuit (20) comprising:
- a substrate of semiconductive material;
- a first circuit environment (CE_1) made from said substrate, comprising a first pair of power supply terminals (VDD1,GND1) to receive a first power supply voltage applicable between said terminals (VDD1,GND1) and also comprising an output terminal (ou1);
- a second circuit environment (CE_2) made from said substrate, comprising a second pair of power supply terminals (VDD2,GND2), distinct from said first pair of terminals (VDD1,GND1), to receive a second power supply voltage applicable between terminals of said second pair and also comprising an input terminal (In2) electrically coupled with said output terminal (Ou1).
The integrated circuit comprises a device for protecting from electrostatic discharges comprising an integrated resistive device (Rcd) connected between said output terminal (Ou1) and said input terminal (In2).

Abstract translation: 集成电路（20），包括： - 半导体材料的基板; - 第一电路环境（CE_1）从所述基板制成的，包括：第一对供电端子（VDD1，GND1）中以接收适用所述端子（VDD1，GND1），因此，其包括输出端之间的第一电源电压（OU1 ）; - 第二电路环境（CE_2）从所述基板制成，包括第二对电源端子（VDD 2，GND2），从所述第一对端子（VDD1，GND1）中，不同的接收适用端子之间的第二电源电压 所述第二对等包括电耦合到所述输出端子（OU1）输入端（IN2）的。 该集成电路包括一个装置用于从静电放电包括集成电阻性装置（RCD），其连接所述输出端子（OU1）之间的保护和所述输入端（IN2）。

公开(公告)号：EP1458102A1

公开(公告)日：2004-09-15

申请号：EP03425160.3

申请日：2003-03-14

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Nicollini, Germano ,  Martignone, Ricardo

IPC: H03M1/68

CPC classification number: H03M1/687 ,  H03M1/68 ,  H03M1/745 ,  H03M1/765

Abstract: The described digital-analog converter comprises a first section (MSB) for converting the more significant bits of a digital code into a first voltage (Vin) of a multiplicity of discrete voltages that are integral multiples of a predetermined first voltage step (ΔV1), a second section (LSB) to convert the less significant bits of the digital code into a current, means for transforming the current (IL) of the second section (LSB) into a second voltage of a multiplicity of discrete voltages that are integral multiples of a second voltage step (ΔV2) equal to 1/2 L of the product of the first voltage step (ΔV1) multiplied by a predetermined coefficient, where L is the number of the less significant bits of the digital code to be converted, control means (DEC-9BIT; TRANSCOD-3BIT) of the first and the second section and summation means (OPA2) for obtaining an output voltage (Vout) that is the sum of the second voltage and the product of the first voltage multiplied by the predetermined coefficient. With a view to obtaining a low consumption, the summation means have resistive feedback means comprising a voltage divider (R3, R4) and the means for transforming the current (IL) into a second voltage comprise a conversion resistor (R4) that forms part of the voltage divider.

Abstract translation: 所描述的数模转换器包括用于将数字代码的更高有效位转换为多个分立电压的第一电压（Vin）的第一部分（MSB），该多个离散电压是预定的第一电压步长（DELTA V1）的整数倍， ，用于将数字代码的较低有效位转换为电流的第二部分（LSB），用于将第二部分（LSB）的电流（IL）变换为多个整数倍的多个离散电压的第二电压的装置 第二电压步长（DELTA V2）等于第一电压步长（DELTA V1）乘以预定系数的乘积的1/2

公开(公告)号：EP1039642A1

公开(公告)日：2000-09-27

申请号：EP99830170.9

申请日：1999-03-24

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Nagari, Angelo ,  Mecchia, Alessandro

IPC: H03M1/06

CPC classification number: H03M1/068 ,  H03M1/0845 ,  H03M1/468 ,  H03M1/804

Abstract: A set (Array_SAR) of sampling capacitors weighted according to a binary code is charged through a first capacitive unit (Array_Vin), whose capacitance is equal to the sum of the capacitances of the set (Array_SAR), at a voltage Vcm-Vin/2. The conversion is carried out by the SAR process by means of a comparator (13') and a logic unit (14') which operates the switches (SW1'-SW6') associated with the capacitors. The final position of the switches is loaded into a register (15') which supplies the digital output signal (Nout). To prevent any disturbances in the power supply and reference potential sources from affecting the accuracy of the conversion, two further capacitive units (Array_-Vref) and (Array_GND) are provided, with the same capacitance as the first capacitive unit, and these make it possible to present all the disturbances at the input of the comparator (13') in common mode and therefore without any effect on the output (OutCmp).

Abstract translation: 根据二进制码加权的采样电容器的集合（Array_SAR）通过电容Vcm-Vin / 2的电容等于集电容（Array_SAR）的电容的第一电容单元（Array_Vin）来充电 。 通过SAR处理，通过比较器（13'）和操作与电容器相关联的开关（SW1'-SW6'）的逻辑单元（14'）进行转换。 开关的最终位置被加载到提供数字输出信号（Nout）的寄存器（15'）中。 为了防止电源和参考电位源的任何干扰影响转换精度，提供了两个另外的电容单元（Array_-Vref）和（Array_GND），具有与第一个电容单元相同的电容，这些使它 可能以共模显示比较器（13'）输入端的所有干扰，因此对输出（OutCmp）没有任何影响。

公开(公告)号：EP0782187B1

公开(公告)日：2000-06-28

申请号：EP95830559.1

申请日：1995-12-29

Applicant: STMicroelectronics S.r.l.

Inventor： Dallavalle, Carlo ,  Confalonieri, Pierangelo

IPC: H01L27/02 ,  H01L23/00

CPC classification number: H01L27/0207

公开(公告)号：EP0698966B1

公开(公告)日：1998-10-07

申请号：EP94830387.0

申请日：1994-07-29

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Nicollini, Germano

IPC: H03K17/687

CPC classification number: H03K17/6872 ,  H03K2217/0018

公开(公告)号：EP2026467A1

公开(公告)日：2009-02-18

申请号：EP07425478.0

申请日：2007-07-30

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Zamprogno, Marco ,  Martignone, Riccardo

IPC: H03M1/06

CPC classification number: H03M1/0648 ,  H03M1/687 ,  H03M1/747

Abstract: A current steering digital-analog converter (1) for converting a digital code (In-cod) into an analog signal (Vout) is described. The converter comprises:
- a substrate of semiconductor material;
- an array (2) of current generators (MD0, MD1, M1-M15) integrated in the substrate;
- a common summation node (NC1) and switching means (3) controllable on the basis of the digital code for connecting/disconnecting the current generators (MD0, MD1, M1-M15) to/from the common summation node (NC1).
The current generators (MD0, MD1, M1-M15) are such as to provide the common summation node (NC1) with currents having a multiple value according to a power of two compared to a unit current value provided to the summation node by a current generator (MD0) of the array (2) of generators (MD0, MD1, M1-M15).
The current generator (MD0) is divided into a base number of modular current generation elements in parallel to one another at least equal to two.

Abstract translation: 描述用于将数字代码（In-cod）转换为模拟信号（Vout）的电流转向数模转换器（1）。 该转换器包括： - 半导体材料的衬底; - 集成在基板中的电流发生器（MD0，MD1，M1-M15）的阵列（2） - 根据用于将电流发生器（MD0，MD1，M1-M15）与公共求和节点（NC1）连接/断开的数字代码可控的公共求和节点（NC1）和切换装置（3）。 电流发生器（MD0，MD1，M1-M15）的目的是为了提供公共求和节点（NC1），该电流具有与通过电流提供给求和节点的单位电流值相比的两倍的功率的多个值 发生器（2）的发生器（MD0）（MD0，MD1，M1-M15）。 电流发生器（MD0）被分成至少等于2的彼此并联的基本数量的模块化电流产生元件。

公开(公告)号：EP1962421A1

公开(公告)日：2008-08-27

申请号：EP07425100.0

申请日：2007-02-23

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Pierangelo ,  Martignone, Riccardo ,  Zamprogno, Marco

IPC: H03H1/02 ,  H03H7/01

CPC classification number: H03H1/02 ,  H03H7/0153 ,  H03H2210/021 ,  H03H2210/025 ,  H03H2210/036 ,  H03H2210/043

Abstract: A calibration circuit (30) for calibrating an adjustable capacitance (C var (REG_BUS)) of a circuit (31) having a time constant depending on said adjustable capacitance, the calibration circuit (30) being such as to output a calibration signal (REG_BUS) carrying information for calibrating said capacitor (C var (REG_BUS)) and including a calibration loop (RC_DEL, DFF, TG_SAR) comprising:
- a controllable capacitance unit (RC_DEL) suitable to receive a control signal (SAR_BUS) and including at least one array of switched capacitors (C_AR1, CAR_2), that can be activated by means of the control signal (SAR_BUS), the unit (RC_DEL) being such as to output a first signal (OUT_DEL) characterized by a parameter depending on the amount of capacitance of the array (C_AR1, CAR_2) activated by the control signal (SAR_BUS);
- a comparison unit (DFF) suitable to receive said first signal (OUT_DEL) to assess whether said parameter meets a preset condition and to output a comparison signal (OUT_DFF) representative of the assessment result;
- a control and timing logic unit (TG_SAR) suitable to receive the comparison signal (OUT_DFF) to change this control signal (SAR_BUS) based on said comparison signal (OUT_DFF),

characterized in that
said first signal (OUT_DEL) is a logic signal and said parameter is a time parameter of said first signal.

Abstract translation: 用于校准（在具有时间常数取决于所述可调电容的电路（31）的可调节的电容（C VAR（REG_BUS））的校准电路（30），所述校准电路（30）被检查，以输出一个校准信号REG_BUS ）携带信息用于校准所述电容器（C VAR（REG_BUS）），并且包括一个校准循环（RC_DEL，DFF，TG_SAR），包括： - 一个可控电容单元（RC_DEL）适合于接收控制信号（SAR_BUS）和包括至少一个 开关电容器（C_AR1，CAR_2）的阵列也可以由控制信号（SAR_BUS），单元（RC_DEL）的方式来激活正被检查，以输出由参数为特征的第一信号（OUT_DEL）上的电容的量根据 由控制信号（SAR_BUS）激活阵列（C_AR1，CAR_2）的; - 一个比较单元（DFF），其适于接收所述第一信号（OUT_DEL）评估是否所述参数是否满足预设条件，并输出比较信号（OUT_DFF）代表评估结果的一个; - 控制和定时逻辑单元（TG_SAR）适合于基于所述比较信号（OUT_DFF）接收比较信号（OUT_DFF）来改变该控制信号（SAR_BUS）表示，在这特点第一信号（OUT_DEL）是一个逻辑信号，并且 所述参数是所述第一信号的时间参数。

公开(公告)号：EP1788704A1

公开(公告)日：2007-05-23

申请号：EP05425812.4

申请日：2005-11-17

Applicant: STMicroelectronics S.r.l.

Inventor： Guanziroli, Federico ,  Nicollini, Germano ,  Confalonieri, Pierangelo

IPC: H03K4/06

CPC classification number: H03K4/066

Abstract: A generating device (100) of a triangular signal (v tri (t)) comprises an input device (101) provided with first terminals (102, 103) in order to receive a first (V A ) and second (GND) potentials and with differential output terminals (104, 105) in order to send an intermediate signal (i int (t)) to an integration device (501).
This integration device comprises differential input terminals (IN1, IN2) connected to the output terminals of the input device and first output terminals (OUT1, OUT2) in order to provide the triangular signal (V tri (t)).
The generating device is characterized in that the input device comprises switching means (T 1 , T 2 , T 3 , T 4 ) which can be activated/deactivated by means of external selection signals (S 1 , S 2 ) in order to connect the input terminals (IN1, IN2) to the first terminals of the input device according to alternative configurations. Furthermore, these external selection signals are generated in response to a timing signal (CK) having a substantially constant frequency (f ck ).

Abstract translation: 三角形信号（v tri（t））的发生装置（100）包括设置有第一端子（102,103）的输入装置（101），以便接收第一（VA）和第二（GND）电位并且与 差分输出端子（104,105），以便向集成装置（501）发送中间信号（int int（t））。 该积分装置包括连接到输入装置的输出端的差分输入端（IN1，IN2）和第一输出端（OUT1，OUT2），以提供三角形信号（V tri（t））。 该生成装置的特征在于，该输入装置包括可通过外部选择信号（S1，S2）激活/去激活的切换装置（T 1，T 2，T 3，T 4），以便连接 输入端子（IN1，IN2）根据其他配置连接到输入设备的第一个端子。 此外，这些外部选择信号是响应于具有基本恒定频率（f ck）的定时信号（CK）产生的。