中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

60 records (took 0.025 seconds)

    Unbalanced latch and fuse circuit including the same
    15.
    发明授权
    Unbalanced latch and fuse circuit including the same 失效
    不平衡锁存电路和含有它们Schmelgsicherungsschatung

    公开(公告)号：EP0756379B1

    公开(公告)日：2003-09-24

    申请号：EP95830337.2

    申请日：1995-07-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pascucci, Luigi ,  Rolandi, Paolo ,  Barcella, Antonio ,  Fontana, Marco

    IPC: H03K3/356 ,  G11C16/06

    CPC classification number: G11C7/20 ,  H03K3/356008 ,  H03K3/356104

    Abstract: A latch circuit (1) that is intentionally imbalanced, so that a first output (6) reaches ground voltage and a second output (7) reaches a supply voltage; and a fully static low-consumption fuse circuit the particularity whereof resides in that it comprises the intentionally unbalanced latch circuit (1) and a reversing branch that comprises the fuse to be programmed (6) and is adapted to reverse the operation of the latch circuit, so that in the virgin state the fuse (9) connects the second output (7) of the latch circuit (1) to the ground voltage and connects the first output (6) to the supply voltage.

    Method for storing and reading data in a multilevel nonvolatile memory with a non-binary number of levels, and architecture therefor
    16.
    发明公开
    Method for storing and reading data in a multilevel nonvolatile memory with a non-binary number of levels, and architecture therefor 有权
    存储和非易失性多电平存储与非二进制数水平的读取数据和对应的电路结构的方法

    公开(公告)号：EP1298670A1

    公开(公告)日：2003-04-02

    申请号：EP01830614.2

    申请日：2001-09-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Rolandi, Paolo

    IPC: G11C11/56

    CPC classification number: G11C19/282 ,  G11C11/5628 ,  G11C11/5642

    Abstract: According to the multilevel programming method, each memory location (10a, 10b) can be programmed at a non-binary number of levels. An integer number of bits, for example 5, is stored in two adjacent memory locations (10a, 10b). To this end, the bits to be stored in the two locations are divided into two sets, wherein the first set defines a binary number of levels higher than the non-binary number of levels. During programming, if the first set of bits to be written corresponds to a number smaller than the non-binary number of levels, the first set of bits is written in the first location and the second set of bits is written in the second location (33, 34); if, instead, it is greater than the non-binary number of levels, the first set of bits is written in the second location and the second set of bits is written in the first location (35, 36). The bits of the first set written in the second location (10b) are stored in different levels with respect to the bits of the second set. Consequently, during reading, first it is verified(42) whether the levels reserved to the first set have been written, and the bits read in the two locations are appropriately associated to the two sets of bits.

    Abstract translation: 。根据多级编程的方法，每个存储器位置（10A，10B）能够以非二进制数电平编程。 位的整数，对于实施例5，被存储在两个相邻的存储单元（10A，10B）。 为此，位被存储在两个位置被分成两组，第一组worin定义比非二进制数的水平更高的水平的一个二进制数。 在编程期间，如果要被写入的第一组比特对应于一个数比所述非二进制数的水平，所述第一组位被写入在所述第一位置和所述第二组被写在第二位置的比特的情况下（ 33，34）; 如果，相反，它是比非二进制数的水平时，第一组位被写入在第二位置和第二组位被写入在所述第一位置（35，36）。 写在第二位置（10b）的所述第一组的位被存储在不同的水平相对于所述第二组的位。 因此，读出期间中，首先验证（42）是否保留给第一组的水平已被写入，并在两个位置读出的位被适当地关联到所述两组位。

    Reading circuit and method for a multilevel non volatile memory
    18.
    发明公开
    Reading circuit and method for a multilevel non volatile memory 有权
    Leseschaltkreis undzugehörigesVerfahrenfürnichtflüchtigenMehrpegel-Speicher

    公开(公告)号：EP1249841A1

    公开(公告)日：2002-10-16

    申请号：EP01830248.9

    申请日：2001-04-10

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pagliato, Mauro ,  Rolandi, Paolo ,  Montanaro, Massimo

    IPC: G11C11/56

    CPC classification number: G11C11/5642 ,  G11C11/56 ,  G11C11/5621 ,  G11C2211/5632

    Abstract: Described herein is an asynchronous serial dichotomic sense amplifier (10) comprising a first comparator stage (12) having a first input receiving the cell current (I CELL ) flowing in the multilevel memory cell (18), the content of which is to be read, a second input receiving a first reference current (I REF2 ), and an output supplying the first of the bits stored in the multilevel memory cell (18); a multiplexer stage (16) having a selection input (16c) connected to the output of the first comparator stage (12), a first signal input (16a) receiving a second reference current (I REF1 ), a second signal input (16b) receiving a third reference current (I REF3 ), and a signal output (16d) selectively connectable to the first or the second signal input (16a, 16b) depending on the logic level present on the selection input (16c); and a second comparator stage (14) having a first input receiving the cell current (I CELL ), a second input connected to the signal output (16d) of the multiplexer stage (16), and an output supplying the second of the bits stored in the multilevel memory cell (18).

    Abstract translation: 读取电路包括异步串行二色读取器（12,14,16）。 读取器包括比较器（12）。 比较器的输出提供存储在多电平存储单元（18）中的一个位。 选择器（16）具有连接到比较器的输出和两个信号输入的选择输入。 选择器具有可选择性地连接到两个信号输入之一的输出，这取决于选择输入上的逻辑电平。 电路还包括第二比较器（14）。 还包括以下独立权利要求：（a）多层存储单元的读取方法。

Patent Agency Ranking