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    Embeddable flash memory system for non-volatile storage of code, data and bit-streams for embedded FPGA configurations
    12.
    发明公开
    Embeddable flash memory system for non-volatile storage of code, data and bit-streams for embedded FPGA configurations 有权
    一个可嵌入的闪存系统用于非易失性存储的代码和数据的比特流的用于嵌入式FPGA配置

    公开(公告)号：EP1443519A1

    公开(公告)日：2004-08-04

    申请号：EP03425057.1

    申请日：2003-01-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pasotti, Marco ,  Borgatti, Michele ,  Rolandi, Pier Luigi

    IPC: G11C5/14 ,  G11C16/30

    CPC classification number: G11C16/30

    Abstract: The present invention relates to a 8Mb application-specific embeddable flash memory. It comprises three content-specific I/O ports and delivers a peak read throughput of 1.2GB/s. The memory is combined with a special automatic programming gate voltage ramp generator circuit, a programming rate of 1 Mbyte/s for non-volatile storage of code, data and embedded FPGA bit stream configurations. The test chip has been designed using a NOR type 0.18µm flash embedded technology with 1.8V power supply, two poly, six metal and memory cell size of 0.35µm 2 .

    Abstract translation: 本发明涉及一种8Mb的特定应用可嵌入闪存。 它包括三项具体内容的I / O端口，并提供1.2GB的/ s的峰值读取吞吐量。 该存储器与一个特殊的自动编程栅电压斜坡发生器电路，1兆字节/秒的代码，数据的非易失性存储和嵌入式FPGA比特流结构的编程速率组合。 测试芯片已使用NOR型快闪嵌入式12时18分微米技术与1.8V电源，二聚设计，六个金属和存储器的12:35微米细胞大小<2>。

    A portable data substrate
    13.
    发明公开
    A portable data substrate 审中-公开
    Ein tragbarerDatenträger

    公开(公告)号：EP1204079A1

    公开(公告)日：2002-05-08

    申请号：EP00830730.8

    申请日：2000-11-03

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pasotti, Marco ,  Fumagalli, Luciano ,  Rolandi, Pier Luigi

    IPC: G07F7/10 ,  G07C9/00 ,  G06K9/00

    CPC classification number: G07F7/1008 ,  G06Q20/341 ,  G06Q20/3576 ,  G06Q20/40145 ,  G07C9/00087

    Abstract: A portable data substrate with protection against unauthorized access, comprising: a first non-volatile memory (11) containing protected data, a second non-volatile memory (17) containing identification data of at least one user authorized to have access to the protected data, means (12) for the input of personal data, and processing means (10) connected to the first memory, to the second memory, and to the input means in order to perform a procedure of identification and authorization for access to the protected data by a comparison between the personal data input and the identification data stored. Both the identification data and the personal data comprise data representing a fingerprint and the input means comprises a fingerprint sensor (12) which derives the personal data from a fingerprint of a finger applied to the sensor.

    Abstract translation: 一种具有防止未经授权的访问的便携式数据基板，包括：包含受保护数据的第一非易失性存储器（11），包含被授权访问受保护数据的至少一个用户的标识数据的第二非易失性存储器（17） ，用于输入个人数据的装置（12），连接到第一存储器的处理装置（10），第二存储器和输入装置，以执行用于访问受保护数据的识别和授权的过程 通过个人数据输入与存储的识别数据之间的比较。 识别数据和个人数据都包括表示指纹的数据，并且输入装置包括指纹传感器（12），其从施加到传感器的手指的指纹导出个人数据。

    Device for reading nonvolatile memory cells, in particular analog flash memory cells
    14.
    发明公开
    Device for reading nonvolatile memory cells, in particular analog flash memory cells 有权
    An ere ere ere en en en en en en en en en en en en en en en en en en en en

    公开(公告)号：EP0997912A1

    公开(公告)日：2000-05-03

    申请号：EP98830626.2

    申请日：1998-10-20

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pasotti, Marco ,  Canegallo, Roberto ,  Guaitini, Giovanni ,  Rolandi, Pier Luigi

    IPC: G11C27/00 ,  G11C16/06 ,  G11C11/56

    CPC classification number: G11C16/34 ,  G11C7/16 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/26 ,  G11C27/005 ,  G11C2211/5642

    Abstract: The reading device (1) comprises an A/D converter (8) of n+m bits receiving an input signal (V1) correlated to the threshold voltage (VTH) of the memory cell (2), and supplying a binary output word (WT) of n+m bits. The A/D converter (8) is of a double conversion stage type (8), wherein a first A/D conversion stage (10) carries out a first analog/digital conversion of the input signal (V1), to supply at the output a first intermediate binary word (W1) of n bits, and the second A/D conversion stage (16) can be activated selectively to carry out a second analog/digital conversion of a difference signal (VD) correlated to the difference between the input signal (V1) and the value of the first intermediate binary word (W1). The second A/D conversion stage (16) generates at the output a second intermediate binary word (W2) of m bits supplied, with the first intermediate binary word (W1), to an adder (20) generating the binary output word (WT) of n+m bits.

    Abstract translation: 读取装置（1）包括接收与存储单元（2）的阈值电压（VTH）相关的输入信号（V1）的n + m位的A / D转换器（8），并且提供二进制输出字 WT）n + m位。 A / D转换器（8）是双转换级（8），其中第一A / D转换级（10）执行输入信号（V1）的第一模/数转换，以在 输出n位的第一中间二进制字（W1），并且可以选择性地激活第二A / D转换级（16），以对与第一中间二进制字（W1）之间的差相关的差信号（VD）进行第二模/数转换 输入信号（V1）和第一中间二进制字（W1）的值。 第二A / D转换级（16）在输出端产生与第一中间二进制字（W1）一起提供的m位的第二中间二进制字（W2）到生成二进制输出字（WT）的加法器（20） ）n + m位。

    Method for parallel programming of nonvolatile memory devices, in particular flash memories and EEPROMs
    15.
    发明公开
    Method for parallel programming of nonvolatile memory devices, in particular flash memories and EEPROMs 失效
    对于中并行编程的非易失性存储设备，特别是闪存EEPROM的和方法

    公开(公告)号：EP0913835A1

    公开(公告)日：1999-05-06

    申请号：EP97830550.6

    申请日：1997-10-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Canegallo, Roberto ,  Chioffi, Ernestina ,  Pasotti, Marco ,  Gerna, Danilo ,  Rolandi, Pier Luigi

    IPC: G11C16/06

    CPC classification number: G11C16/3459 ,  G11C16/3454

    Abstract: The programming method comprises the steps of applying a programming pulse to a first cell (2) and simultaneously verifying the present threshold value of at least a second cell (2); then verifying the present threshold value of the first cell and simultaneously applying a programming pulse to the second cell. In practice, during the entire programming operation, the gate terminal of both the cells is biased to a same predetermined gate voltage (V PCX ) and the source terminal is connected to ground; the step of applying a programming pulse is carried out by biasing the drain terminal of the cell to a predetermined programming voltage (V P ) and the step OF verifying is carried out by biasing the drain terminal of the cell to a read voltage (V R ) different from the programming voltage. Thereby, switching between the step of applying a programming pulse and verifying is obtained simply by switching the drain voltage of the cells.

    Abstract translation: 该编程方法包括施加编程脉冲到第一小区（2），并同时验证至少一个第二小区（2）的本阈值的工序; 然后验证所述第一小区的当前阈值，并且同时施加编程脉冲到所述第二小区。 在实践中，整个编程操作期间，这两个单元的栅极端子被偏置到一个相同的栅极预定电压（VPCX）和源极端子连接到地; 施加编程脉冲的步骤是通过偏置单元的漏极端子至预定编程电压（VP）和检验步骤是通过偏置单元的漏极端子的读出电压（VR）不同开展开展 从编程电压。 由此，施加编程脉冲的步骤和验证之间的切换通过切换单元的漏极电压简单地获得。

    A reconfigurable signal processor with embedded flash memory device
    17.
    发明公开
    A reconfigurable signal processor with embedded flash memory device 审中-公开
    Rekonfigurierbarer Signalprozessor mit eingebettetem Flashspeicher

    公开(公告)号：EP1443417A1

    公开(公告)日：2004-08-04

    申请号：EP03425054.8

    申请日：2003-01-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Borgatti, Michele ,  Cali, Lorenzo ,  Lertora, Francesco ,  Pasotti, Marco ,  Rolandi, Pier Luigi

    IPC: G06F15/78 ,  G11C16/30

    CPC classification number: G06F15/7867 ,  G11C16/30 ,  Y02D10/12 ,  Y02D10/13

    Abstract: The present invention relates to a dynamically reconfigurable processing unit (1) including an embedded Flash memory device (3) for non-volatile storage of code, data and bit-streams, the unit (1) being integrated into a single chip together with a microprocessor (2) core. Advantageously, the processing unit further comprises an S-RAM based embedded FPGA unit structured for FPGA reconfigurations having a specific programming interface (7) connected to a port (FP) of said Flash memory device (4) through a DMA channel (8).

    Abstract translation: 本发明涉及一种包括用于代码，数据和比特流的非易失性存储的嵌入式闪存设备（3）的动态可重配置处理单元（1），该单元（1）与 微处理器（2）核心。 有利地，处理单元还包括基于S-RAM的嵌入式FPGA单元，其被构造用于具有通过DMA通道（8）连接到所述闪存设备（4）的端口（FP））的特定编程接口（7）的FPGA重新配置。

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