Abstract:
The invention concerns a method of avoiding disturbance during an erasing steps of an electrically programmable and erasable, semiconductor integrated non-volatile memory device, which comprises a matrix of memory cells divided into sectors. An operation of parallel erasing several sectors of the matrix as well as an operation of verifying the erasing of each sector in the matrix are carried out.
Abstract:
A circuit (300) is proposed for driving a memory line (110) controlling at least one memory cell (105) of a non-volatile memory device (100), the circuit being responsive to a first and a second selection signals, each one suitable to assume a first logic value or a second logic value, wherein the circuit includes a first level shifter (120s) for converting the first selection signal into a first operative signal and a second level shifter (120g) for converting the second selection signal into a second operative signal, each level shifter including first shifting means (210s, 210g) for shifting one of the logic values of the corresponding selection signal to a first bias voltage, and a selector (140) for applying the first operative signal or a second bias voltage to the memory line according to the second operative signal; in the circuit of the invention each level shifter further includes second shifting means (305s, 305g) for shifting another of the logic values of the corresponding selection signal to the second bias voltage.
Abstract:
A non-volatile memory device (120) is proposed. The non-volatile memory device includes a flash memory (205) and means (225) for executing external commands, the external commands including a first subset of commands for accessing the flash memory directly; the memory device further includes a programmable logic unit (245) and means (250) for storing program code for the logic unit, the external commands including a second subset of at least one command for causing the logic unit to process information stored in at least one portion of the flash memory under the control of the program code.