公开(公告)号：EP1489622B1

公开(公告)日：2007-08-15

申请号：EP03425390.6

申请日：2003-06-16

Applicant: STMicroelectronics S.r.l.

Inventor： Resta, Claudio ,  Bedeschi, Ferdinando ,  Pellizzer, Fabio ,  Casagrande, Giulio

IPC: G11C11/34

CPC classification number: G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

公开(公告)号：EP1067605A1

公开(公告)日：2001-01-10

申请号：EP99830431.5

申请日：1999-07-05

Applicant: STMicroelectronics S.r.l.

Inventor： Casagrande, Giulio ,  Zambrano, Raffaele

IPC: H01L27/115 ,  H01L21/8242

CPC classification number: H01L27/11502 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/11507

Abstract: A memory cell (2) integrated in a semiconductor substrate (3) and comprised of a MOS device (4) connected in series to a capacitive element (5), wherein

the MOS device (4) has first and second conduction terminals (6),
the capacitive element (5) has a lower electrode (16) covered with a layer (17) of a dielectric material and coupled capacitively to an upper electrode (18),
said MOS device (4) is overlaid by at least one metallization layer (10,13), which metallization layer (10,13) is covered with at least one top insulating layer (11,14), that the capacitive element (5) is formed on the top insulating layer (11,14), and that said metallization layer (10,13) extends only between said MOS device (4) and said capacitive element (5).

Abstract translation: 一种集成在半导体衬底（3）中并由与电容元件（5）串联连接的MOS器件（4）组成的存储单元（2），其中MOS器件（4）具有第一和第二导电端子（6） ，所述电容元件（5）具有被电介质材料的层（17）覆盖并且电容地耦合到上电极（18）的下电极（16），所述MOS器件（4）被至少一个金属化层 （10,13），所述金属化层（10,13）被至少一个顶部绝缘层（11,14）覆盖，所述电容元件（5）形成在顶部绝缘层（11,14）上，以及 所述金属化层（10,13）仅在所述MOS器件（4）和所述电容元件（5）之间延伸。

公开(公告)号：EP1178491A1

公开(公告)日：2002-02-06

申请号：EP00830553.4

申请日：2000-08-02

Applicant: STMicroelectronics S.r.l.

Inventor： Gastaldi, Roberto ,  Cappelletti, Paolo ,  Casagrande, Giulio ,  Campardo, Giovanni ,  Micheloni, Rino

IPC: G11C16/16 ,  G11C16/34

CPC classification number: G11C16/3431 ,  G11C16/16 ,  G11C16/34

Abstract: A semiconductor memory, particularly of the electrically programmable and erasable type such as a flash memory, comprises at least one two-dimensional array (SCT) of memory cells (MC) with a plurality of rows (row0-row511) and a plurality of columns (COL) of memory cells. The columns of the two-dimensional array are grouped in a plurality of packets (CP0-CP1), and the memory cells belonging to the columns of each packet are formed in a respective semiconductor region (4) with a first type of conductivity, this region (4) being distinct from the semiconductor regions (4) with the first type of conductivity in which the memory cells belonging to the columns of the remaining packets are formed. The semiconductor regions with the first type of conductivity divide the set of memory cells belonging to each row into a plurality of subsets of memory cells that constitute elemental memory units which can be modified individually. It is thus possible to produce memory units of very small dimensions (for example, bytes, words, or long words) which can be erased individually, without excessive overhead in terms of area.

Abstract translation: 半导体存储器，特别是诸如闪存的电可编程和可擦除类型的半导体存储器包括至少一个具有多个行（行0-行511）和多个列的存储器单元（MC）的二维阵列（SCT） （COL）的存储单元。 二维阵列的列被分组为多个分组（CP0-CP1），并且属于每个分组的列的存储器单元以第一类型的导电率形成在相应的半导体区域（4）中，这 区域（4）与半导体区域（4）不同，其中形成属于剩余包的列的存储器单元的第一导电类型。 具有第一导电类型的半导体区域将属于每行的存储器单元组划分为构成可以单独修改的基本存储器单元的多个存储器单元子集。 因此可以产生非常小尺寸的存储单元（例如，字节，单词或长单词），其可以单独擦除，而没有面积方面的过度开销。