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    METHOD AND DEVICE FOR PROCESSING DATA
    11.
    发明专利
    METHOD AND DEVICE FOR PROCESSING DATA 失效

    公开(公告)号：JPH03129523A

    公开(公告)日：1991-06-03

    申请号：JP18255290

    申请日：1990-07-10

    Applicant: TANDEM COMPUTERS INC

    Inventor： ROBAATO DABURIYUU HOOSUTO ,  ROBAATO ERU JIYAADEIIN

    IPC: G06F7/499 ,  G06F7/00 ,  G06F7/53 ,  G06F11/14

    Abstract: PURPOSE: To detect errors with simple constitution by giving an error signal when a first operation result for first and second operands and a second operation result for third and fourth operands are not equal. CONSTITUTION: A redundant multiplication result is transferred from a COU output register 36 to the scratch register 50b of a register file 50 or from the register to either J or K register 54 or 56 in a data device 18. At the same time, an (shifted) initial result is transferred from a scratch path (SPAD) 64 to the other J or K register 54 or 56. The contents of the two registers are exclusively OR-processed by an arithmetic and logic unit(ALU) 58. The result is monitored by a zero detection circuit 70 and a comparison processing is executed. When the error is detected, a series of other means is given and the error becomes a multiplication error. Thus, the error can be detected with simple constitution.

    METHOD AND SYSTEM FOR PROCESSING EXCEPTION
    12.
    发明专利
    METHOD AND SYSTEM FOR PROCESSING EXCEPTION 失效

    公开(公告)号：JPH03116236A

    公开(公告)日：1991-05-17

    申请号：JP13513890

    申请日：1990-05-24

    Applicant: TANDEM COMPUTERS INC

    Inventor： ROBAATO ERU JIYAADEIIN ,  SHIYANON JIEI RINCHI ,  FUIRITSUPU AARU MANERA ,  ROBAATO DABURIYUU HOOSUTO

    IPC: G06F9/38

    Abstract: PURPOSE: To simplify a system by activating an exception procedure developed for a signal instruction by a unique exception processing procedure. CONSTITUTION: An exception display test bit field generated by an ALU is connected with the input of a latched MUX 110, a control port is connected with the control field of a microcode in a level 5, and the output is connected with a second input port of an AND gate 106. The output of a first decoder DEC I flashes a pipe line and inhibits the writing operation of a level 5 when an exception condition is discovered. The MUX 110 transmits a specific exception display test bit to be tested about an instruction family during execution, and when the exception condition is generated, the AND gate 106 is opened, a microcode filed of (m) bits in a level 5 is decoded, and a control signal for executing a non-paring restarting procedure execution is generated. Thus, the system can be simplified.

    INTEGRATED CIRCUIT ARCHITECTURE OF LINEAR ARRAY WAFER SCALE
    13.
    发明专利
    INTEGRATED CIRCUIT ARCHITECTURE OF LINEAR ARRAY WAFER SCALE 失效

    公开(公告)号：JPH0369138A

    公开(公告)日：1991-03-25

    申请号：JP11567490

    申请日：1990-05-01

    Applicant: TANDEM COMPUTERS INC

    Inventor： ROBAATO DABURIYUU HOOSUTO

    IPC: H01L21/82 ,  G11C29/00 ,  H03K19/173

    Abstract: PURPOSE: To obtain a simplified architecture adapting to use to form a linear array by connecting it with a digital system array by incorporating input bus means and output bus means at boundaries in cells, and incorporating specific selecting means, logic means and control means in a cell structure. CONSTITUTION: A cell 10 is formed to have N boundaries. Each boundary has an input bus means and an output bus means. A structure of the cell 10 has a selecting means 12 corresponding to each boundary and having a plurality of selective inputs and one selective output connected to receive the input bus means and output bus means of the corresponding boundary to couple the selective output of the (N-1) boundaries to the output bus means of relative adjacent boundary to be operable to select the input bus means or the output bus means; a logic means 20 connected between the residual selecting means 12 and the output bus means of relative adjacent boundary to perform a logical function; and a control means 22 coupled to the respective means 12 to select one of a plurality of selective inputs to the respective means 12.

    LARGE-SCALE MULTIPROCESSOR SYSTEM WITH NETWORK BETWEEN FAULT-TOLERANT PROCESSORS
    17.
    发明专利
    LARGE-SCALE MULTIPROCESSOR SYSTEM WITH NETWORK BETWEEN FAULT-TOLERANT PROCESSORS 失效

    公开(公告)号：JPH0844683A

    公开(公告)日：1996-02-16

    申请号：JP3636995

    申请日：1995-02-24

    Applicant: TANDEM COMPUTERS INC

    Inventor： ROBAATO DABURIYUU HOOSUTO

    IPC: G06F11/00 ,  G06F15/80 ,  G06F15/16 ,  G06F15/173

    Abstract: PURPOSE: To construct a large-scaled parallel processing system with a band width which can be used for access to data held by the system in which each processor unit has high availability. CONSTITUTION: A large-scaled parallel processor is constituted by connecting many individual processor units. Plural processor parts 12 including one or plural processor units mutually connected for data communication by a redundant bus mechanism is formed. Then, the processor parts 12 are mutually connected by a toroidal constitution, and the array of horizontal and vertical rows is formed. Each processor part 12 is connected with the four adjacent processor parts 12 through dual communication paths 14 and 16. Thus, at least two individual paths are provided for data communication from one arbitrary processor unit to another arbitrary processor unit. Each processor unit includes an individual input/output bus mechanism which can be used for mutually connecting the processor part array in extension to three dimension.

    MICROINSTRUCTION SEQUENCER
    19.
    发明专利
    MICROINSTRUCTION SEQUENCER 失效

    公开(公告)号：JPH03230222A

    公开(公告)日：1991-10-14

    申请号：JP32516190

    申请日：1990-11-27

    Applicant: TANDEM COMPUTERS INC

    Inventor： ROBAATO DABURIYUU HOOSUTO ,  MAIZANUA EMU RAAMAN ,  RICHIYAADO HARISU

    IPC: G06F9/22 ,  G06F9/26 ,  G06F9/28

    Abstract: PURPOSE: To perform 2-cycle RAM access without sacrificing performance by using the first and second banks of a control memory and storing micro- instructions. CONSTITUTION: A calculation system 10 is provided with a macroinstruction processor (IPU) 14 for storing and taking out macroinstructions, this micro- instruction sequencer 22 for generating the micro-instructions corresponding to the macro-instructions stored inside the IPU 14 and a data processor (DPU) 26 for storing and processing data corresponding to instructions from the IPU 14 and the micro-instruction sequencer 22. Then, the micro-instruction sequencer 22 communicates with the IPU 14 and the DPU 26 respectively through an IPU-sequencer bus 30 and a DPU-sequencer bus 36. Also, the IPU 14 communicates with the DPU 26 through an IPU-DPU bus 37. Thus, the DPU 26 starts the execution of the micro-instruction at a rank 1 while a first micro- instruction is executed at the rank 2.

    SYSTEM AND METHOD FOR PROCESSING INSTRUC- TION OF DATA PROCESSOR
    20.
    发明专利
    SYSTEM AND METHOD FOR PROCESSING INSTRUC- TION OF DATA PROCESSOR 失效

    公开(公告)号：JPH03116233A

    公开(公告)日：1991-05-17

    申请号：JP13513790

    申请日：1990-05-24

    Applicant: TANDEM COMPUTERS INC

    Inventor： ROBAATO DABURIYUU HOOSUTO

    IPC: G06F9/26 ,  G06F9/38

    Abstract: PURPOSE: To improve an instruction processing capability by transmitting the family of instructions including an instruction in the format of collation to an ALU and a memory in one clock. CONSTITUTION: First and second instructions in an instruction family are stored in pipe line registers ROF and ROS 20 and 18, decoded by decoders 22 and 24, and the decoded results are outputted to DCO buses 28 and 30. Then, status information from the both decoded results is transmitted to a pairing logical devices PLU control port 26 on status buses 32 and 34. This is used for a processor which uses one stack as the data source and data sink of the ALU (arithmetic and logical unit) processing. Thus, a capability can be improved by the parallel processing capability of the instruction family of this system.

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