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    MANUFACTURE OF SEMICONDUCTOR DEVICE FOR MAKING SELF-ALIGNED LOCAL INTERCONNECTION WHICH IS SELF-ALIGNED
    12.
    发明专利
    MANUFACTURE OF SEMICONDUCTOR DEVICE FOR MAKING SELF-ALIGNED LOCAL INTERCONNECTION WHICH IS SELF-ALIGNED 失效

    公开(公告)号：JPH11191623A

    公开(公告)日：1999-07-13

    申请号：JP9206298

    申请日：1998-04-03

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： SUN SHIH-WEI

    IPC: H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L27/04 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To manufacture a semiconductor device in an integrated process for making a self-aligned borderless contact of the element and a self-aligned local interconnection of the element. SOLUTION: A substrate 30 having a plurality of shallow trench insulating layers 31 is formed, first and second gate electrodes are respectively formed on a locally interconnected region 9" and an active region 9', source and drain regions 36 are formed through ion-implantation in the substrate 30 with the use of these first and second gate electrodes as masks, first spacers 37a, 37b and second spacers 37c, 37d are respectively formed at the peripheries first, and the second gate electrodes and the exposed parts of gate oxide films are removed. Self-aligned silicide films 42a to 42c are respectively formed on the surfaces of the regions 36, second insulating layers are formed, dielectric layers 35a,... are respectively formed on the second insulating layers and for making a self-aligned borderless contact and making a self-aligned local interconnection, a first opening is equipped on the region 9" and a second opening is equipped on the region 9'.

    LOW POWER CMOS PROCESS AND STRUCTURE
    13.
    发明专利
    LOW POWER CMOS PROCESS AND STRUCTURE 失效

    公开(公告)号：JPH11186404A

    公开(公告)日：1999-07-09

    申请号：JP35278697

    申请日：1997-12-22

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： SUN SHIH-WEI

    IPC: H01L21/8238 ,  H01L27/092

    Abstract: PROBLEM TO BE SOLVED: To miniaturize an FET by selectively operating proper ion implantation to an active device area. SOLUTION: A device insulating part 32 is formed by an LOCOS method on a substrate 30, and the upper face is covered with a thick dialectic layer. Next, a gate electrode part 48 is etched, and a gate oxide layer 44 is formed at a substrate exposed part on the bottom face. Then, a channel part is formed by proper ion implantation through a gate electrode opening 48, and polysilicon is accumulated so that a gate electrode 48 can be formed. The thick dielectric layer is removed, a source/drain area 50 is doping formed, and an oxidized spacer 52 is formed at the gate electrode side face by CVD.

    CHEMICALLY/MECHANICALLY POLISHING METHOD USING SLURRY MIXTURE OF LOW PH VALUE
    14.
    发明专利
    CHEMICALLY/MECHANICALLY POLISHING METHOD USING SLURRY MIXTURE OF LOW PH VALUE 失效

    公开(公告)号：JPH11186200A

    公开(公告)日：1999-07-09

    申请号：JP34664497

    申请日：1997-12-16

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： YO MEISEI ,  WU JUAN-YUAN ,  RO KATETSU ,  SUN SHIH-WEI

    IPC: H01L21/304 ,  C09K3/14 ,  H01L21/321

    Abstract: PROBLEM TO BE SOLVED: To enable CMP process of tungsten with the same polishing pad and the same polishing station, by polishing a dielectric layer after polishing process of a metal layer, and setting pH values of first slurry mixed solution and second slurry mixed solution in the respective specified ranges. SOLUTION: In a process, a chemically/mechanically polishing method is contained, a dielectric layer is formed, and at least one via of a through hole is formed in the dielectric layer. A tungsten layer is formed in the via and on the dielectric layer. In order to eliminate the tungsten layer form the dielectric layer, first slurry 42 having oxidizing component whose pH value is about 2-4 is used, and first chemically/mechanically polishing process is performed. By using second slurry whose pH value is about 2-4, second chemically/ mechanically polishing processing is performed, and the dielectric layer is polished.

    FORMATION OF INCREASED CAPACITANCE
    15.
    发明专利
    FORMATION OF INCREASED CAPACITANCE 失效

    公开(公告)号：JPH11163260A

    公开(公告)日：1999-06-18

    申请号：JP30673497

    申请日：1997-11-10

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： YEW TRI-RUNG ,  RO KATETSU ,  SUN SHIH-WEI

    IPC: H01L27/04 ,  H01L21/822

    Abstract: PROBLEM TO BE SOLVED: To increase the charge conservation capability of an integrated-circuit capacitor, which can be utilized in a memory, and to provided increased conservation capability even though the manufacturing cost is decreased at the same time. SOLUTION: This method is for forming the increased capacitance for the charge conservation structure of an integrated-circuit device and includes the following processes. In a first process, access circuits 16 and 18, which control access to the electrode of the charge conservation structure through an electrode contact 22, are formed on a substrate 10. In a second process, a first conducting layer 36 is formed on a substrate 10 under the contact state with the electrode contact 22. In a third process, a dielectric material layer 42 is formed on the first conducting layer 36. In a fourth process, the layer of polysilicon particles 40 is formed on the dielectric material layer 42, and a non-covered part is made to remain between the particles. In a fifth process, these exposed parts of the dielectric material layer 42 are selectively removed, and column bodies 42 of the dielectric material are formed with an interval which is provided on these columnar bodies 42. In a sixth process, a second conducting layer 44 is formed on these columnar bodies 42. In a seventh process, a capacitor layer 44 is formed on these columnar bodies 42. In a eigth process, a capacitor dielectric layer 46 is formed on the second dielectric layer 44. In a last process, a third dielectric layer 50 is formed on the capacitor dielectric layer 46.

    MANUFACTURING METHOD OF SEMISPHERICAL SILICON CRYSTALLINE PARTICLE STRUCTURE
    16.
    发明专利
    MANUFACTURING METHOD OF SEMISPHERICAL SILICON CRYSTALLINE PARTICLE STRUCTURE 失效

    公开(公告)号：JPH11121718A

    公开(公告)日：1999-04-30

    申请号：JP1051198

    申请日：1998-01-22

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： YEW TRI-RUNG ,  RO KATETSU ,  SUN SHIH-WEI ,  SHIH HSUEH-HAO

    IPC: C23C16/04 ,  C23C16/24 ,  H01L21/02 ,  H01L21/205 ,  H01L21/285 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To obtain the capacitor storage node of an integrated circuit by a method wherein the title semispherical silicon crystalline particle structure is selectively formed by the chemical vapor phase synthetic process producing a by-product using chlorosilane as a precursor. SOLUTION: A substrate 20 having silicon oxide layers 24 and a contact hole 22 passing through them 24 is prepared while the contact hole 22 is filled up with polycystalline silicon so as to form a contact plug. After the formation of a polycrystalline silicon layer 26 on the contact hole 22 and the silicon oxide layers 24, the polycrystalline silicon layer 26 is patterned to form a lower part electrode. Next, silicon crystalline particles are grown using chlorosilane as a precursor. At this time the nuclear growth of silicon on the polycrystalline silicon layer 26 rapidly advances while the etching away speed of silicon by HCl is slower than that of HSG-Si structure but the silicon nuclear growth on the silicon oxide layers 24 takes a long time thereby raking the formation of the HSG-Si structure selectable.

    FORMATION OF INTEGRATED CIRCUIT
    17.
    发明专利
    FORMATION OF INTEGRATED CIRCUIT 失效

    公开(公告)号：JPH1168052A

    公开(公告)日：1999-03-09

    申请号：JP21521897

    申请日：1997-08-08

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： SUN SHIH-WEI ,  SAI MOKIN

    IPC: H01L27/08

    Abstract: PROBLEM TO BE SOLVED: To form a gate oxide of different thickness easily on a single chip by implanting a dopant into a first region and a dopant of different dosage into a second region thereby growing an oxide in the first region and an oxide of different thickness in the second region. SOLUTION: Nitrogen ions are implanted into the surface of a substrate in section A through a pad-like oxide layer 26 until a dosage of about 5×10 /cm is reached, for example. The silicon surface in section A implanted with nitrogen ions is then exposed to an oxidizing atmosphere and a gate oxide layer of about 40Å is grown on the surface of the substrate. Subsequently, nitrogen ions are implanted into section B of the substrate 10 through the exposed pad-like oxide layer 26. Nitrogen ions are implanted at a dosage of 2×10 /cm , for example. Subsequently, the silicon surface in section B implanted with nitrogen ions is exposed to an oxidizing atmosphere and a gate oxide layer of about 75Å is formed.

    Barrier layer for a semiconductor device
    19.
    发明专利
    Barrier layer for a semiconductor device 未知

    公开(公告)号：GB2341484A

    公开(公告)日：2000-03-15

    申请号：GB9819997

    申请日：1998-09-14

    Applicant: UNITED MICROELECTRONICS CORP

    Inventor： YEW TRI-RUNG ,  LUR WATER ,  SUN SHIH-WEI ,  HUANG YIMIN

    IPC: H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78 ,  H01L21/285 ,  H01L21/3205 ,  H01L23/532

    Abstract: A method for forming a barrier layer for a semiconductor device comprises the steps of first providing a semiconductor substrate 30 that has a conductive layer 31 already formed thereon. Then, a dielectric layer 32 such as an organic low-k dielectric layer is deposited over the conductive layer 31 and the semiconductor substrate 30. Next, an opening 33 is formed in the dielectric layer 32 exposing the conductive layer 31. Thereafter, a first barrier 34 layer is deposited into the opening 33 and the surrounding area. The first barrier layer 34 can be a silicon-containing layer or a doped silicon (doped-Si) layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method, a low-pressure chemical vapor deposition (LPCVD) method, an electron beam evaporation method or a sputtering method. Finally, a second barrier layer 35 is formed over the first barrier layer 34, e.g. by CVD. The second barrier layer 35 can be a titanium/titanium nitride (Ti/TiN) layer, a tungsten nitride (WN) layer, a tantalum (Ta) layer or a tantalum nitride (TaN) layer. The opening is then filled with tungsten, copper or aluminium to form a via 36. The method can be applied to a damascene process.

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